JPS56138324A - J-k flip-flop circuit - Google Patents

J-k flip-flop circuit

Info

Publication number
JPS56138324A
JPS56138324A JP4156380A JP4156380A JPS56138324A JP S56138324 A JPS56138324 A JP S56138324A JP 4156380 A JP4156380 A JP 4156380A JP 4156380 A JP4156380 A JP 4156380A JP S56138324 A JPS56138324 A JP S56138324A
Authority
JP
Japan
Prior art keywords
gates
output signals
fed
composite
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4156380A
Other languages
Japanese (ja)
Other versions
JPS6035850B2 (en
Inventor
Masataka Hirasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55041563A priority Critical patent/JPS6035850B2/en
Publication of JPS56138324A publication Critical patent/JPS56138324A/en
Publication of JPS6035850B2 publication Critical patent/JPS6035850B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Abstract

PURPOSE:To increase the reliability of FF, by avoiding the malfunction when noise is mixed to the input signal, through the negative feedback of the output signal of J-KFF to the input and the supply of NAND gates on the way of the composite logic circuit of FF. CONSTITUTION:J-KFF circuit consists of the master FF10 and slave FF20, and FF10 consists of the composite logic circuits 3, 6 consisting of NAND gates 1, 4, NOR gates 2, 5 and AND gates 31, 32, and the output signals -QM, QM are respectively fed to the gates 31, 32. FF20 consists of the composite inversion logic circuits 13, 16 consisting of OR gates 11, 14 and NAND gates 12, 15. Further, the output signals QS, -QS are negative-fed-back to the input side of FF10 and fed to the gates 31, 32 on the way of the circuits 3, 6, to prevent the malfunction when noise is mixed to the input signal, allowing to increase the reliability of the output signals Q, Q' of FF.
JP55041563A 1980-03-31 1980-03-31 J-K flip-flop circuit Expired JPS6035850B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55041563A JPS6035850B2 (en) 1980-03-31 1980-03-31 J-K flip-flop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55041563A JPS6035850B2 (en) 1980-03-31 1980-03-31 J-K flip-flop circuit

Publications (2)

Publication Number Publication Date
JPS56138324A true JPS56138324A (en) 1981-10-28
JPS6035850B2 JPS6035850B2 (en) 1985-08-16

Family

ID=12611903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55041563A Expired JPS6035850B2 (en) 1980-03-31 1980-03-31 J-K flip-flop circuit

Country Status (1)

Country Link
JP (1) JPS6035850B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5921122A (en) * 1982-06-30 1984-02-03 ウエスターン・エレクトリック・カンパニー，インコーポレーテッド Set/reset master/slave flip-flop circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5921122A (en) * 1982-06-30 1984-02-03 ウエスターン・エレクトリック・カンパニー，インコーポレーテッド Set/reset master/slave flip-flop circuit

Also Published As

Publication number Publication date
JPS6035850B2 (en) 1985-08-16

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