JPS56136067A - Multiple-value transmission system - Google Patents

Multiple-value transmission system

Info

Publication number
JPS56136067A
JPS56136067A JP3905780A JP3905780A JPS56136067A JP S56136067 A JPS56136067 A JP S56136067A JP 3905780 A JP3905780 A JP 3905780A JP 3905780 A JP3905780 A JP 3905780A JP S56136067 A JPS56136067 A JP S56136067A
Authority
JP
Japan
Prior art keywords
data
frequency divider
code
synchronism
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3905780A
Other languages
Japanese (ja)
Inventor
Toshiro Kato
Kenji Ogami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP3905780A priority Critical patent/JPS56136067A/en
Publication of JPS56136067A publication Critical patent/JPS56136067A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H04L25/4923—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes
    • H04L25/4925—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes using balanced bipolar ternary codes

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To improve synchronism characteristics by inserting an inhibition word of an (m)-value code as a frame pulse into a signal by speed conversion, obtained after converting a signal into the M-digit (m)-value code and by decreasing the probability of occurrence of pseudo frame synchronism without performing word synchronization previously. CONSTITUTION:Series data A from input terminal 12 is written in (n)-bit memory circuit 10 with write pulses (phi1)-(phin) from 1/n frequency divider 14, and the written data is read successively with read pulses (phi1')-(phin') from 1/n frequency divider 16 and applied to four-bit memory 26. Then, data phase-synchronized by frequency divider 16, phase comparator 18 and VCO20 constituting a PLL circuit is converted into ternary code by 4B/3T converting circuit 30. Into this code-converted data, an inhibition word is inserted by speed conversion by frame counter 22, 1/3 frequency divider 32, NAND gates 34-1-34-6, etc., and the obtained data is applied to unipolar/bipolar converting circuit 40, decreasing the probability of the occurrence of pseudo frame synchronism.
JP3905780A 1980-03-28 1980-03-28 Multiple-value transmission system Pending JPS56136067A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3905780A JPS56136067A (en) 1980-03-28 1980-03-28 Multiple-value transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3905780A JPS56136067A (en) 1980-03-28 1980-03-28 Multiple-value transmission system

Publications (1)

Publication Number Publication Date
JPS56136067A true JPS56136067A (en) 1981-10-23

Family

ID=12542496

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3905780A Pending JPS56136067A (en) 1980-03-28 1980-03-28 Multiple-value transmission system

Country Status (1)

Country Link
JP (1) JPS56136067A (en)

Similar Documents

Publication Publication Date Title
IL50913A (en) Sequential digital word detector
GB1444216A (en) D/a converter for pcm
US4307381A (en) Method and means for encoding and decoding digital data
GB1053189A (en)
GB1396923A (en) Data communication system
JPS56136067A (en) Multiple-value transmission system
GB1294731A (en) Bivalent signal transmission system
US3283255A (en) Phase modulation system for reading particular information
US3703609A (en) Noise signal generator for a digital speech synthesizer
US3697699A (en) Digital speech signal synthesizer
JPS6281850A (en) Detecting method for minimum bit in reception data
GB1512086A (en) Pcm transmission system
JPS56166654A (en) Pulse stuffing synchronizer
JPS53136423A (en) Network point processing system for picture signal
ES426518A1 (en) Compander for TDM telecommunication system
ES475088A1 (en) Decoder for binary coded data
GB1444323A (en) Device for deriving a frame synchronisation signal from a received binary data series flow having a given bit repetition rate a repetitive but unknown structure and a synchronisation bit in a particular time slot in each frame
SU1109808A1 (en) Dynamic storage
JPS55132157A (en) Frame-synchronous pattern detecting circuit
SU1270787A2 (en) Device for performing digital magnetic recording
HOLMES The influence of glottal waveform on the naturalness of speech from a parallel-formant synthesizer(Computer simulated parallel-formant synthesizer to copy short samples of human speech)
SU1524048A1 (en) Random number generator
GB1374735A (en) Telegraph transmission apparatus
SU1385318A1 (en) Frequency-manipulated signal receiver
SU1338093A1 (en) Device for tracking code sequence delay