JPS56125829A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56125829A
JPS56125829A JP2791380A JP2791380A JPS56125829A JP S56125829 A JPS56125829 A JP S56125829A JP 2791380 A JP2791380 A JP 2791380A JP 2791380 A JP2791380 A JP 2791380A JP S56125829 A JPS56125829 A JP S56125829A
Authority
JP
Japan
Prior art keywords
base metal
resist
metal
semiconductor device
photomask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2791380A
Other languages
Japanese (ja)
Inventor
Toshikazu Kamoshita
Tatsuo Shimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Power Semiconductor Device Ltd
Original Assignee
Hitachi Ltd
Hitachi Haramachi Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Haramachi Electronics Ltd filed Critical Hitachi Ltd
Priority to JP2791380A priority Critical patent/JPS56125829A/en
Publication of JPS56125829A publication Critical patent/JPS56125829A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To enable to form an electrode by performing a simple positioning for the subject semiconductor device by a method wherein, after the mask consisting of a photoresist is fixed on the base metal surface, a plurality of base metal is exposed by performing an exposure, a developing and a baking, and a metal is attached using an immersion method. CONSTITUTION:On the entire main surface of the semiconductor 1 covered by the base metal 2, a dryfilm photoresist 7 is laminated using a roller press-fitting method. Then, a photomask 8 is placed on the resist 7. At this time, a positioning is performed in such manner that the opaque section to be formed on the photomask 8 will be coincided with the base metal 2. Then, the hole corresponding to the wiring of the base metal 2 is formed on the resist 7 by performing the exposure, developing and baking. Successively, in the state wherein the resist 7 is coated, the above is immersed in a solder vessel and the bump of a metal 10 is attached. lastly, the resist 7 is removed. Through these procedures, an electrode can be formed in a short time by performing a simple positioning.
JP2791380A 1980-03-07 1980-03-07 Manufacture of semiconductor device Pending JPS56125829A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2791380A JPS56125829A (en) 1980-03-07 1980-03-07 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2791380A JPS56125829A (en) 1980-03-07 1980-03-07 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56125829A true JPS56125829A (en) 1981-10-02

Family

ID=12234116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2791380A Pending JPS56125829A (en) 1980-03-07 1980-03-07 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56125829A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7745075B2 (en) * 2006-03-09 2010-06-29 Au Optronics Corp. Method for fabricating color filter substrates

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7745075B2 (en) * 2006-03-09 2010-06-29 Au Optronics Corp. Method for fabricating color filter substrates

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