JPS56124200A - Test method for semiconductor memory - Google Patents

Test method for semiconductor memory

Info

Publication number
JPS56124200A
JPS56124200A JP1648781A JP1648781A JPS56124200A JP S56124200 A JPS56124200 A JP S56124200A JP 1648781 A JP1648781 A JP 1648781A JP 1648781 A JP1648781 A JP 1648781A JP S56124200 A JPS56124200 A JP S56124200A
Authority
JP
Japan
Prior art keywords
address
memory
ram
fail
swap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1648781A
Other languages
Japanese (ja)
Other versions
JPS6135638B2 (en
Inventor
Shigeki Nozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1648781A priority Critical patent/JPS56124200A/en
Publication of JPS56124200A publication Critical patent/JPS56124200A/en
Publication of JPS6135638B2 publication Critical patent/JPS6135638B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To mask defective bits easily and surely at the comparison test time and to simplify the test, by addressing the fail memory through the address switching part provided with an address swapping part. CONSTITUTION:The address output from address pattern generator APG is caused to pass through address switching part AE provided with the address swapping part as it is in case of a normal address but is converted to a swap address through part AE in case of the swap mode, and this address accesses RAM to be tested and fail memory FM, where defective bit positions are stored with the high level, simultaneously. Consequently, the same corresponding address positions of RAM and memory FM are accessed independently of the mode of the address; and if the fail state is written in memory FM once, the mask operation to inhibit the comparison between the read value of RAM and the expected value in comparator CMP for defective bits is performed easily and surely even if addresses are switched thereafter.
JP1648781A 1981-02-06 1981-02-06 Test method for semiconductor memory Granted JPS56124200A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1648781A JPS56124200A (en) 1981-02-06 1981-02-06 Test method for semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1648781A JPS56124200A (en) 1981-02-06 1981-02-06 Test method for semiconductor memory

Publications (2)

Publication Number Publication Date
JPS56124200A true JPS56124200A (en) 1981-09-29
JPS6135638B2 JPS6135638B2 (en) 1986-08-14

Family

ID=11917637

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1648781A Granted JPS56124200A (en) 1981-02-06 1981-02-06 Test method for semiconductor memory

Country Status (1)

Country Link
JP (1) JPS56124200A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5317573A (en) * 1989-08-30 1994-05-31 International Business Machines Corporation Apparatus and method for real time data error capture and compression redundancy analysis

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5317573A (en) * 1989-08-30 1994-05-31 International Business Machines Corporation Apparatus and method for real time data error capture and compression redundancy analysis

Also Published As

Publication number Publication date
JPS6135638B2 (en) 1986-08-14

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