JPS56122231A - Mean value output type a and d converter - Google Patents
Mean value output type a and d converterInfo
- Publication number
- JPS56122231A JPS56122231A JP2495880A JP2495880A JPS56122231A JP S56122231 A JPS56122231 A JP S56122231A JP 2495880 A JP2495880 A JP 2495880A JP 2495880 A JP2495880 A JP 2495880A JP S56122231 A JPS56122231 A JP S56122231A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- capacitor
- counter
- delivers
- charged
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/52—Input signal integrated with linear return to datum
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
PURPOSE:To convert the mean value of the input signal into a digital quanity, by counting the time during which an integration is given to the input signal for an optional time and then discharging it with the reference voltage to secure the 0-level. CONSTITUTION:The input voltage Vi is charged to the capacitor C1 via the switch circuits 5 and 6, and the charged electric charge is put into the integrator 10 to deliver the voltage Vo. The comparator 11 delivers the signal ec=1 when receiving an application of the signal Vo. Then the control circuit 14 delivers the signal er=1 after the time T0 to switch the switching circuit 5; and at the same time delivers the signal eR=1 to apply it to the AND circuit 15 and then puts the clock pulse Pc into the counter 16. The electric charge that is charged to the capacitor C2 of the integrator 10 is transferred to the capacitor C1 to be discharged successively. When the electric charge is discharged completely, the output Vo turns to zero. Thus the output ec of the comparator 11 becomes 0, and the thus no clock pulse Pc is put into the counter 16 any more. Then the count value of the counter 16 becomes to a value that is proportional to the input voltage Vi.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2495880A JPS56122231A (en) | 1980-02-29 | 1980-02-29 | Mean value output type a and d converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2495880A JPS56122231A (en) | 1980-02-29 | 1980-02-29 | Mean value output type a and d converter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56122231A true JPS56122231A (en) | 1981-09-25 |
Family
ID=12152482
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2495880A Pending JPS56122231A (en) | 1980-02-29 | 1980-02-29 | Mean value output type a and d converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56122231A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0555916A (en) * | 1991-08-28 | 1993-03-05 | Shimadzu Corp | A/d conversion method |
-
1980
- 1980-02-29 JP JP2495880A patent/JPS56122231A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0555916A (en) * | 1991-08-28 | 1993-03-05 | Shimadzu Corp | A/d conversion method |
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