JPS56116183A - Processing system for binary picture - Google Patents
Processing system for binary pictureInfo
- Publication number
- JPS56116183A JPS56116183A JP1889580A JP1889580A JPS56116183A JP S56116183 A JPS56116183 A JP S56116183A JP 1889580 A JP1889580 A JP 1889580A JP 1889580 A JP1889580 A JP 1889580A JP S56116183 A JPS56116183 A JP S56116183A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- line
- line density
- fine
- picture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/41—Bandwidth or redundancy reduction
- H04N1/411—Bandwidth or redundancy reduction for the transmission or storage or reproduction of two-tone pictures, e.g. black and white pictures
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Facsimile Image Signal Circuits (AREA)
- Image Processing (AREA)
- Editing Of Facsimile Originals (AREA)
Abstract
PURPOSE:To transmit the binary picture with shrinked line width and line density and to pick up original picture at reception side with enlargement, by providing fine line circuit, line density shrink circuit, line density extension circuit and line thick circuit. CONSTITUTION:The video signal from the input terminal 11 is rejected for the unevenness added with facsimile picture isolated points of white video elements at the smoothing circuit 12 and fed to the fine line circuit 13. The fine line circuit 13 shrinks uniformly the line width of longitudinal, transversal and skew lines of facsimile picture and adds the video information which is made fine, to the line density shrinking circuit 14, where the line density is shrinked and the result is fed again to the circuit 15. The fine line circuit 15 is operated to reject redundancy more and transmits the result via the code conversion circuit 16. At the reception side, decoding is made at the decoding conversion circuit 18 and the line density is enlarged at the line density enlarging circuit 19 and the size of original picture with enlargement is picked up via the line thick circuit 21.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1889580A JPS56116183A (en) | 1980-02-18 | 1980-02-18 | Processing system for binary picture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1889580A JPS56116183A (en) | 1980-02-18 | 1980-02-18 | Processing system for binary picture |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56116183A true JPS56116183A (en) | 1981-09-11 |
Family
ID=11984300
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1889580A Pending JPS56116183A (en) | 1980-02-18 | 1980-02-18 | Processing system for binary picture |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56116183A (en) |
-
1980
- 1980-02-18 JP JP1889580A patent/JPS56116183A/en active Pending
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