JPS56116154A - Interrupting detection circuit - Google Patents

Interrupting detection circuit

Info

Publication number
JPS56116154A
JPS56116154A JP1922380A JP1922380A JPS56116154A JP S56116154 A JPS56116154 A JP S56116154A JP 1922380 A JP1922380 A JP 1922380A JP 1922380 A JP1922380 A JP 1922380A JP S56116154 A JPS56116154 A JP S56116154A
Authority
JP
Japan
Prior art keywords
interruption
request
signals
circuit
produced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1922380A
Other languages
Japanese (ja)
Inventor
Mamoru Maeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP1922380A priority Critical patent/JPS56116154A/en
Publication of JPS56116154A publication Critical patent/JPS56116154A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To enable processing in the order of occurronce of interruption, by using the interruption storange circuit. CONSTITUTION:Interruption request signals IR0-IR7 are input to the interruption mask circuit 3, and the request signal RQ is produced when the interruption request is present. The counter decoder 5 is counted up with the clock signal CK, the count output COUNT is given on the one hand to the interruption storage circuit 4 and on the other hand, it is decoded at the decode section to produce the strobe signals STB0-STB7. The strobe signals are given to the interruption mask circuit 3 to sequentially scan the presence of input of interruption request signal. With this state, when either one of the interruption request signals is produced, the request signal RQ is produced from the interruption mask circuit 3 in synchronizing with the strobe signal corresponding to the request signals IR0-IR7, and the interruption storage circuit 4 fetches the content of the count output COUNT at the time and stores it.
JP1922380A 1980-02-20 1980-02-20 Interrupting detection circuit Pending JPS56116154A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1922380A JPS56116154A (en) 1980-02-20 1980-02-20 Interrupting detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1922380A JPS56116154A (en) 1980-02-20 1980-02-20 Interrupting detection circuit

Publications (1)

Publication Number Publication Date
JPS56116154A true JPS56116154A (en) 1981-09-11

Family

ID=11993362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1922380A Pending JPS56116154A (en) 1980-02-20 1980-02-20 Interrupting detection circuit

Country Status (1)

Country Link
JP (1) JPS56116154A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0228730A (en) * 1988-04-04 1990-01-30 Hitachi Ltd System and device for controlling priority

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0228730A (en) * 1988-04-04 1990-01-30 Hitachi Ltd System and device for controlling priority

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