JPS5611556A - Data transfer control system - Google Patents

Data transfer control system

Info

Publication number
JPS5611556A
JPS5611556A JP8771179A JP8771179A JPS5611556A JP S5611556 A JPS5611556 A JP S5611556A JP 8771179 A JP8771179 A JP 8771179A JP 8771179 A JP8771179 A JP 8771179A JP S5611556 A JPS5611556 A JP S5611556A
Authority
JP
Japan
Prior art keywords
data
period
logical
count
bit group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8771179A
Other languages
Japanese (ja)
Inventor
Satoshi Nochida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8771179A priority Critical patent/JPS5611556A/en
Publication of JPS5611556A publication Critical patent/JPS5611556A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable to reduce the burden over the software, by determining the sampling period of the data succeeding to the control bit group, based on the logical value stored in the buffer register, count value and data prepared in advance.
CONSTITUTION: The time for every time of specified every logical period of the control bit group at the head of the data transferred from the device 301 is counted by the counter 107, and the count of every given logical period and the logical value of every count period of the counter 107 are tentatively stored in the buffer register 108. Further, based on the logical value stored in the buffer register 108 and the data, of which the count value is prepared in advance, the sampling period of the data succeeding to the control bit group is determined by the device controller 302 by the control logic. Thus, the burden to the software can be reduced.
COPYRIGHT: (C)1981,JPO&Japio
JP8771179A 1979-07-11 1979-07-11 Data transfer control system Pending JPS5611556A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8771179A JPS5611556A (en) 1979-07-11 1979-07-11 Data transfer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8771179A JPS5611556A (en) 1979-07-11 1979-07-11 Data transfer control system

Publications (1)

Publication Number Publication Date
JPS5611556A true JPS5611556A (en) 1981-02-04

Family

ID=13922484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8771179A Pending JPS5611556A (en) 1979-07-11 1979-07-11 Data transfer control system

Country Status (1)

Country Link
JP (1) JPS5611556A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6804732B2 (en) 2002-03-29 2004-10-12 Denso Corporation Port sampling circuit apparatus incorporated in a microcomputer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6804732B2 (en) 2002-03-29 2004-10-12 Denso Corporation Port sampling circuit apparatus incorporated in a microcomputer

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