JPS56112159A - Circuit interrupting device - Google Patents

Circuit interrupting device

Info

Publication number
JPS56112159A
JPS56112159A JP1579380A JP1579380A JPS56112159A JP S56112159 A JPS56112159 A JP S56112159A JP 1579380 A JP1579380 A JP 1579380A JP 1579380 A JP1579380 A JP 1579380A JP S56112159 A JPS56112159 A JP S56112159A
Authority
JP
Japan
Prior art keywords
host
circuit
data
terminal
sent out
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1579380A
Other languages
Japanese (ja)
Inventor
Toshiaki Maruyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP1579380A priority Critical patent/JPS56112159A/en
Publication of JPS56112159A publication Critical patent/JPS56112159A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus

Abstract

PURPOSE:To enable an efficient transmission by transmitting data to an imaginary terminal of a circuit in place of a host prior to occurrence of overflow of process data of a host computer in the host side. CONSTITUTION:A host 1 and a terminal 2 are connected through a semidouble circuit. The data sent from the host 1 is sent out to a circuit 4 through an OR gate 7, and the data sent from the terminal 2 is sent out to the circuit 4 through an AND gate 6, and the two are not sent out simultaneously. A circuit interrupting device 5 is attached to above-mentioned host 1. This device 5 transmits the data to an imaginary terminal in the circuit 4 in place of the host prior to occurrence of overflow of process data in the host computer 11. By this, data transmission from the terminal 2 is interrupted momentarily and, consequently, transmission is made effectively.
JP1579380A 1980-02-12 1980-02-12 Circuit interrupting device Pending JPS56112159A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1579380A JPS56112159A (en) 1980-02-12 1980-02-12 Circuit interrupting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1579380A JPS56112159A (en) 1980-02-12 1980-02-12 Circuit interrupting device

Publications (1)

Publication Number Publication Date
JPS56112159A true JPS56112159A (en) 1981-09-04

Family

ID=11898707

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1579380A Pending JPS56112159A (en) 1980-02-12 1980-02-12 Circuit interrupting device

Country Status (1)

Country Link
JP (1) JPS56112159A (en)

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