JPS56111187A - Memory control circuit - Google Patents

Memory control circuit

Info

Publication number
JPS56111187A
JPS56111187A JP1009580A JP1009580A JPS56111187A JP S56111187 A JPS56111187 A JP S56111187A JP 1009580 A JP1009580 A JP 1009580A JP 1009580 A JP1009580 A JP 1009580A JP S56111187 A JPS56111187 A JP S56111187A
Authority
JP
Japan
Prior art keywords
rom
address
power supply
rank bits
roms
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1009580A
Other languages
Japanese (ja)
Inventor
Takao Nouchi
Yoshiaki Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1009580A priority Critical patent/JPS56111187A/en
Publication of JPS56111187A publication Critical patent/JPS56111187A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards

Landscapes

  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To make uniform ROM access even with small transition space of address, by making specified allocation of power supply to ROM via a ROM selection circuit with lower rank bits of readout address. CONSTITUTION:When a microprocessor 1 outputs the readout address corresponding to the address of ROM for the upper rank bits to the memory bus 3, the lower rank bits of the readout address are decoded with a ROM selection circuit 10, and every time when the address is advanced, the power supply switch 4'-1... selectively connect the connection of allocation to the power supply line 6, allowing to access ROMs 2-1... sequentially. Thus, even if the transition space of address spaces 8-1... is small, ROMs 2-1... are uniformly accessed, heat dissipation is uniformed, and the heat dissipation of ROM 2-1... is substantially lowered to increase the reliability and ROM can be made to high density.
JP1009580A 1980-02-01 1980-02-01 Memory control circuit Pending JPS56111187A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1009580A JPS56111187A (en) 1980-02-01 1980-02-01 Memory control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1009580A JPS56111187A (en) 1980-02-01 1980-02-01 Memory control circuit

Publications (1)

Publication Number Publication Date
JPS56111187A true JPS56111187A (en) 1981-09-02

Family

ID=11740762

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1009580A Pending JPS56111187A (en) 1980-02-01 1980-02-01 Memory control circuit

Country Status (1)

Country Link
JP (1) JPS56111187A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6050696A (en) * 1983-08-27 1985-03-20 Shinko Electric Co Ltd Memory circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6050696A (en) * 1983-08-27 1985-03-20 Shinko Electric Co Ltd Memory circuit

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