DE3779618D1 - SEMICONDUCTOR MEMORY WITH CELL ARRANGEMENT. - Google Patents

SEMICONDUCTOR MEMORY WITH CELL ARRANGEMENT.

Info

Publication number
DE3779618D1
DE3779618D1 DE8787119215T DE3779618T DE3779618D1 DE 3779618 D1 DE3779618 D1 DE 3779618D1 DE 8787119215 T DE8787119215 T DE 8787119215T DE 3779618 T DE3779618 T DE 3779618T DE 3779618 D1 DE3779618 D1 DE 3779618D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
cell arrangement
cell
arrangement
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787119215T
Other languages
German (de)
Other versions
DE3779618T2 (en
Inventor
Machio Segawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE3779618D1 publication Critical patent/DE3779618D1/en
Application granted granted Critical
Publication of DE3779618T2 publication Critical patent/DE3779618T2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
DE8787119215T 1986-12-25 1987-12-24 SEMICONDUCTOR MEMORY WITH CELL ARRANGEMENT. Expired - Fee Related DE3779618T2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61309763A JPS63161596A (en) 1986-12-25 1986-12-25 Semiconductor memory device

Publications (2)

Publication Number Publication Date
DE3779618D1 true DE3779618D1 (en) 1992-07-09
DE3779618T2 DE3779618T2 (en) 1993-01-21

Family

ID=17996977

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787119215T Expired - Fee Related DE3779618T2 (en) 1986-12-25 1987-12-24 SEMICONDUCTOR MEMORY WITH CELL ARRANGEMENT.

Country Status (4)

Country Link
US (1) US4875193A (en)
EP (1) EP0282650B1 (en)
JP (1) JPS63161596A (en)
DE (1) DE3779618T2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910009444B1 (en) * 1988-12-20 1991-11-16 삼성전자 주식회사 Semiconductor memory device
KR940007639B1 (en) * 1991-07-23 1994-08-22 삼성전자 주식회사 Data transmitting circuit having divided input/output line
US5732010A (en) * 1992-09-22 1998-03-24 Kabushiki Kaisha Toshiba Dynamic random access memory device with the combined open/folded bit-line pair arrangement
US5796671A (en) 1996-03-01 1998-08-18 Wahlstrom; Sven E. Dynamic random access memory
JP5404584B2 (en) * 2010-11-19 2014-02-05 株式会社東芝 Semiconductor memory device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5942399B2 (en) * 1979-12-21 1984-10-15 株式会社日立製作所 memory device
EP0166642A3 (en) * 1984-05-30 1989-02-22 Fujitsu Limited Block-divided semiconductor memory device having divided bit lines
JPS6194296A (en) * 1984-10-16 1986-05-13 Fujitsu Ltd Semiconductor memory
EP0180054A3 (en) * 1984-10-31 1988-05-11 Texas Instruments Incorporated Dual ended adaptive folded bitline scheme
US4745577A (en) * 1984-11-20 1988-05-17 Fujitsu Limited Semiconductor memory device with shift registers for high speed reading and writing

Also Published As

Publication number Publication date
DE3779618T2 (en) 1993-01-21
JPS63161596A (en) 1988-07-05
EP0282650B1 (en) 1992-06-03
US4875193A (en) 1989-10-17
EP0282650A1 (en) 1988-09-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee