JPS56109033A - Da conversion method - Google Patents

Da conversion method

Info

Publication number
JPS56109033A
JPS56109033A JP1074680A JP1074680A JPS56109033A JP S56109033 A JPS56109033 A JP S56109033A JP 1074680 A JP1074680 A JP 1074680A JP 1074680 A JP1074680 A JP 1074680A JP S56109033 A JPS56109033 A JP S56109033A
Authority
JP
Japan
Prior art keywords
converter
bit
rank
fed
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1074680A
Other languages
Japanese (ja)
Inventor
Masaru Ohashi
Takao Namae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jeol Ltd
Original Assignee
Jeol Ltd
Nihon Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jeol Ltd, Nihon Denshi KK filed Critical Jeol Ltd
Priority to JP1074680A priority Critical patent/JPS56109033A/en
Publication of JPS56109033A publication Critical patent/JPS56109033A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To enable the DA conversion in high speed with high resolution, by giving the lower-rank n-bit signal to the 1st DA converter and the upper-rank (k-n)- bit signal to the 2nd DA converter and memory, and outputting the signal compensating the error of the 2nd DA converter from the memory. CONSTITUTION:Among k-bit digital signals from a digital signal generator, the lower-rank n-bit signal is fed to a converter DAC10 having n-bit resolution, + or -(1/ 2beta)LSB accuracy, Vn maximum output voltage, and the upper-rank (k-n)-bit signal is fed to a converter DAC20 having m-bit resolution, + or -(1/2)LSB and Vk maximum output voltage, and memory 2, respectively. Further, the data compensating the error of DAC20 in this memory 2 is fed to a converter DAC30, having p-bit resolution, and + or -(1/2)LSB accuracy. Further, the output of each converter DAC is fed to an adder 3. Thus, DA conversion in high speed with high resolution can be made.
JP1074680A 1980-01-31 1980-01-31 Da conversion method Pending JPS56109033A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1074680A JPS56109033A (en) 1980-01-31 1980-01-31 Da conversion method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1074680A JPS56109033A (en) 1980-01-31 1980-01-31 Da conversion method

Publications (1)

Publication Number Publication Date
JPS56109033A true JPS56109033A (en) 1981-08-29

Family

ID=11758865

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1074680A Pending JPS56109033A (en) 1980-01-31 1980-01-31 Da conversion method

Country Status (1)

Country Link
JP (1) JPS56109033A (en)

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