JPS56109031A - Da conversion method - Google Patents

Da conversion method

Info

Publication number
JPS56109031A
JPS56109031A JP1074580A JP1074580A JPS56109031A JP S56109031 A JPS56109031 A JP S56109031A JP 1074580 A JP1074580 A JP 1074580A JP 1074580 A JP1074580 A JP 1074580A JP S56109031 A JPS56109031 A JP S56109031A
Authority
JP
Japan
Prior art keywords
bits
adder
converters
rank
conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1074580A
Other languages
Japanese (ja)
Inventor
Masaru Ohashi
Takao Namae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jeol Ltd
Original Assignee
Jeol Ltd
Nihon Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jeol Ltd, Nihon Denshi KK filed Critical Jeol Ltd
Priority to JP1074580A priority Critical patent/JPS56109031A/en
Publication of JPS56109031A publication Critical patent/JPS56109031A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To enable the DA conversion with high resolution by using a plurality of DA converters in high speed, by adding the upper-rank 2 bits from a digital data generator with the signal of lower rank-8 bits from the gate circuit for DA conversion. CONSTITUTION:A digital data generator 1 inputs the lower-rank 8 bits among 10 bits of data to gate circuits G1-G4 in parallel, respectively, and the upper-rank 2 bits are fed to a decoder 2 and an adder 3. Further, the decoder 2 controls the output state of the circuits G1-G4 based on the 2-bit signal from the generator 1. Further, the adder 3 adds the 2 bits from the generator 1 with the 8-bit signal from the gate circuit G4 and feeds the result to the converter DAC40. The output of the circuits G1-G3 is respectively fed to converters DAC10, 20, 30, the adder 4 adds the output of converters DAC10, 20, 30, 40 and the analog output of the adder 4 is converted into a voltage signal with an amplifier not shown. Thus, a plurality of high-speed DA converters are used for DA conversion of high resolution.
JP1074580A 1980-01-31 1980-01-31 Da conversion method Pending JPS56109031A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1074580A JPS56109031A (en) 1980-01-31 1980-01-31 Da conversion method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1074580A JPS56109031A (en) 1980-01-31 1980-01-31 Da conversion method

Publications (1)

Publication Number Publication Date
JPS56109031A true JPS56109031A (en) 1981-08-29

Family

ID=11758838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1074580A Pending JPS56109031A (en) 1980-01-31 1980-01-31 Da conversion method

Country Status (1)

Country Link
JP (1) JPS56109031A (en)

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