JPS56107392A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS56107392A
JPS56107392A JP1072380A JP1072380A JPS56107392A JP S56107392 A JPS56107392 A JP S56107392A JP 1072380 A JP1072380 A JP 1072380A JP 1072380 A JP1072380 A JP 1072380A JP S56107392 A JPS56107392 A JP S56107392A
Authority
JP
Japan
Prior art keywords
write
potential
resistor
power supply
storage device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1072380A
Other languages
Japanese (ja)
Other versions
JPS6043589B2 (en
Inventor
Hidetsune Kurokawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55010723A priority Critical patent/JPS6043589B2/en
Publication of JPS56107392A publication Critical patent/JPS56107392A/en
Publication of JPS6043589B2 publication Critical patent/JPS6043589B2/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4094Bit-line management or control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To make unnecessary the clear operation and to enable the clear indication of failures in write-in system circuit, by precharging with a given potential different from the precharge potential at write-in and readout for the memory cell in matrix arrangement, at the application of power supply. CONSTITUTION:When the storage device is in stable state with power supply, FF110 is set, a transistor Q1 connected to a resistor R1 of a precharge control circuit 180 is OFF, Q3, Q4 are ON, and the transistor Q1 connected to the resistor R2 the same as the resistor R1 of the circuit 181 is OFF. Thus, at the write-in and readout when FF110 of wirings 210, 211 via transistors 30, 31 is reset, one potential, which is equal normally, is lower or higher than other. The cell 10 and the like in matrix arrangement selected with this precharge potential is initially set to 1 or 0 corresponding to different potential of the lines 210, 211 independently of the previous memory content. Thus, the clear operation of memory cell at the application of power supply is made unnecessary and failure in the write-in system circuit at initial stage can clearly be depicted.
JP55010723A 1980-01-30 1980-01-30 semiconductor storage device Expired JPS6043589B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55010723A JPS6043589B2 (en) 1980-01-30 1980-01-30 semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55010723A JPS6043589B2 (en) 1980-01-30 1980-01-30 semiconductor storage device

Publications (2)

Publication Number Publication Date
JPS56107392A true JPS56107392A (en) 1981-08-26
JPS6043589B2 JPS6043589B2 (en) 1985-09-28

Family

ID=11758199

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55010723A Expired JPS6043589B2 (en) 1980-01-30 1980-01-30 semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS6043589B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6148193A (en) * 1984-08-13 1986-03-08 Fujitsu Ltd Semiconductor memory device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61175136U (en) * 1985-04-17 1986-10-31

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6148193A (en) * 1984-08-13 1986-03-08 Fujitsu Ltd Semiconductor memory device

Also Published As

Publication number Publication date
JPS6043589B2 (en) 1985-09-28

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