JPS56105581A - Slice level generating system - Google Patents
Slice level generating systemInfo
- Publication number
- JPS56105581A JPS56105581A JP713180A JP713180A JPS56105581A JP S56105581 A JPS56105581 A JP S56105581A JP 713180 A JP713180 A JP 713180A JP 713180 A JP713180 A JP 713180A JP S56105581 A JPS56105581 A JP S56105581A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- output
- video
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V10/00—Arrangements for image or video recognition or understanding
- G06V10/20—Image preprocessing
- G06V10/28—Quantising the image, e.g. histogram thresholding for discrimination between background and foreground patterns
Abstract
PURPOSE:To obtain an accurate video shaping signal by storing white level voltages respectively independently for the respective sensor cells of a sensor circuit thereby decreasing the effect of the variance in sensitivity or the variance in illumination of an optical system owing to the positions of sensors. CONSTITUTION:When the cells of a sensor circuit 12 scan the place of a medium 302 where there are no marks, a video signal 113 is outputted from an amplifier circuit 13, and enter as input to a comparator 19 and a voltage follower circuit 14. Here, the voltage follower circuits 14, 15 compare the video signal 113 and the signal 116 from a voltage dividing circuit 17 and output the either of the signals having a higher voltage as a white level signal 114. When the power source is turnd on, all the storage contents of an analog register 16 are 0V, hence the output signal 115 of the register 16 and the output signal 116 of the circuit 17 are both 0V and therefore while the sensor circuit 12 is making scanning, the video signal 113 is straightly the white level signal, which is stored in the register 16 in synchronization with the clock signal 111. The video shaping circuit 118 which is the output of the output of the comparator 19 maintains ''0''.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP713180A JPS56105581A (en) | 1980-01-24 | 1980-01-24 | Slice level generating system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP713180A JPS56105581A (en) | 1980-01-24 | 1980-01-24 | Slice level generating system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56105581A true JPS56105581A (en) | 1981-08-22 |
Family
ID=11657517
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP713180A Pending JPS56105581A (en) | 1980-01-24 | 1980-01-24 | Slice level generating system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56105581A (en) |
-
1980
- 1980-01-24 JP JP713180A patent/JPS56105581A/en active Pending
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