JPS5599651A - Microprogram control type data processor - Google Patents

Microprogram control type data processor

Info

Publication number
JPS5599651A
JPS5599651A JP797479A JP797479A JPS5599651A JP S5599651 A JPS5599651 A JP S5599651A JP 797479 A JP797479 A JP 797479A JP 797479 A JP797479 A JP 797479A JP S5599651 A JPS5599651 A JP S5599651A
Authority
JP
Japan
Prior art keywords
branch
destination address
selection circuits
branch destination
designated field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP797479A
Other languages
Japanese (ja)
Inventor
Shinji Oga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP797479A priority Critical patent/JPS5599651A/en
Publication of JPS5599651A publication Critical patent/JPS5599651A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To realize plural units of multi-direction branch orders without increasing the bit width by designating the specified bit group of the unused branch destination address designated field and the selecting one of plural units of test circuits.
CONSTITUTION: Test results 50 and 51 which are selected via lower-rank two bits A4 and A5 of branch destination address designated field 30 are transmitted to branch destination address selection circuits 26 and 27 among the test results supplied to test result selection circuits 24 and 25 within arithmetic control circuit 5. And address lines 64 and 65 are selected in the case of the single-direction branch order designation via selection order 66 of branch conditions designated field 31; while output 50 and 51 of test result selection circuits 24 and 25 in the case of the multi-direction branch order designation respectively. At the same time, output 70 and 71 of selection circuits 26 and 27 are sent to address register 4, and then all bits of register 4 are filled up to decide the branch destination address.
COPYRIGHT: (C)1980,JPO&Japio
JP797479A 1979-01-25 1979-01-25 Microprogram control type data processor Pending JPS5599651A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP797479A JPS5599651A (en) 1979-01-25 1979-01-25 Microprogram control type data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP797479A JPS5599651A (en) 1979-01-25 1979-01-25 Microprogram control type data processor

Publications (1)

Publication Number Publication Date
JPS5599651A true JPS5599651A (en) 1980-07-29

Family

ID=11680423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP797479A Pending JPS5599651A (en) 1979-01-25 1979-01-25 Microprogram control type data processor

Country Status (1)

Country Link
JP (1) JPS5599651A (en)

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