JPS559827B1 - - Google Patents
Info
- Publication number
- JPS559827B1 JPS559827B1 JP6524771A JP6524771A JPS559827B1 JP S559827 B1 JPS559827 B1 JP S559827B1 JP 6524771 A JP6524771 A JP 6524771A JP 6524771 A JP6524771 A JP 6524771A JP S559827 B1 JPS559827 B1 JP S559827B1
- Authority
- JP
- Japan
- Prior art keywords
- strip
- cut
- lead frame
- frame
- lengthened
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005538 encapsulation Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12188—All metal or with adjacent metals having marginal feature for indexing or weakened portion for severing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12361—All metal or with adjacent metals having aperture or cut
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T428/12528—Semiconductor component
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US7960270A | 1970-10-09 | 1970-10-09 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS559827B1 true JPS559827B1 (ja) | 1980-03-12 |
Family
ID=22151587
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6524771A Pending JPS559827B1 (ja) | 1970-10-09 | 1971-08-27 |
Country Status (4)
Country | Link |
---|---|
US (1) | US3795492A (ja) |
JP (1) | JPS559827B1 (ja) |
DE (2) | DE2150432C3 (ja) |
NL (1) | NL7113856A (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS511072A (ja) * | 1974-06-21 | 1976-01-07 | Fujitsu Ltd | Jushifujigatahandotaisochino seizohoho |
DE2930760A1 (de) * | 1979-07-28 | 1981-02-12 | Itt Ind Gmbh Deutsche | Verfahren zum umhuellen von halbleiterbauelementen mittels spritzgiessens |
US4504435A (en) * | 1982-10-04 | 1985-03-12 | Texas Instruments Incorporated | Method for semiconductor device packaging |
EP0305589B1 (en) * | 1982-10-04 | 1997-12-17 | Texas Instruments Incorporated | Method and apparatus for the encapsulation of a semiconductor device mounted on a lead-frame |
DE3320700A1 (de) * | 1983-06-08 | 1984-12-13 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum kunststoffumhuellen von elektrischen bauelementen |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1015909A (en) * | 1963-12-30 | 1966-01-05 | Gen Micro Electronics Inc | Method of and product for packaging electronic devices |
US3440027A (en) * | 1966-06-22 | 1969-04-22 | Frances Hugle | Automated packaging of semiconductors |
US3544857A (en) * | 1966-08-16 | 1970-12-01 | Signetics Corp | Integrated circuit assembly with lead structure and method |
US3537175A (en) * | 1966-11-09 | 1970-11-03 | Advalloy Inc | Lead frame for semiconductor devices and method for making same |
US3469684A (en) * | 1967-01-26 | 1969-09-30 | Advalloy Inc | Lead frame package for semiconductor devices and method for making same |
US3436810A (en) * | 1967-07-17 | 1969-04-08 | Jade Corp | Method of packaging integrated circuits |
US3550766A (en) * | 1969-03-03 | 1970-12-29 | David Nixen | Flat electronic package assembly |
US3597666A (en) * | 1969-11-26 | 1971-08-03 | Fairchild Camera Instr Co | Lead frame design |
US3627901A (en) * | 1969-12-19 | 1971-12-14 | Texas Instruments Inc | Composite electronic device package-connector unit |
US3611061A (en) * | 1971-07-07 | 1971-10-05 | Motorola Inc | Multiple lead integrated circuit device and frame member for the fabrication thereof |
-
1970
- 1970-10-09 US US00079602A patent/US3795492A/en not_active Expired - Lifetime
-
1971
- 1971-08-27 JP JP6524771A patent/JPS559827B1/ja active Pending
- 1971-10-08 NL NL7113856A patent/NL7113856A/xx unknown
- 1971-10-09 DE DE2150432A patent/DE2150432C3/de not_active Expired
- 1971-10-09 DE DE19717138302U patent/DE7138302U/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
NL7113856A (ja) | 1972-04-11 |
US3795492A (en) | 1974-03-05 |
DE2150432B2 (de) | 1979-05-23 |
DE7138302U (de) | 1972-01-27 |
DE2150432C3 (de) | 1980-01-10 |
DE2150432A1 (de) | 1972-05-31 |
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