JPS5597654A - Fault record control system - Google Patents

Fault record control system

Info

Publication number
JPS5597654A
JPS5597654A JP524479A JP524479A JPS5597654A JP S5597654 A JPS5597654 A JP S5597654A JP 524479 A JP524479 A JP 524479A JP 524479 A JP524479 A JP 524479A JP S5597654 A JPS5597654 A JP S5597654A
Authority
JP
Japan
Prior art keywords
error
retrial
clock
counter
detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP524479A
Other languages
Japanese (ja)
Inventor
Kazuyuki Tomita
Satoru Nagata
Koji Kusumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP524479A priority Critical patent/JPS5597654A/en
Publication of JPS5597654A publication Critical patent/JPS5597654A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To secure recording for the internal state before detection of the error by counting the clock number at the retrial time and thus discontinuing the clock right before detection of the error.
CONSTITUTION: With detection of the error, error detection latch 10 is turned on. Thus clock counter 50 is reset, and at the same time the first internal state is scanned out. In case the error can be rewritten, switch 20 is turned on for the first retrial to renew retrial counter 30 with gates G2 and G4 opened. Then counter 50 counts the clock number until the retrial is succeeded. When the count number is n and the error factor is identical, the retrial counter is renewed for the 2nd retrial. Thus gate G3 opens, and counting is given to counter 50 by -1 via the clock pulse under retrial. And when the count value becomes in agreement with the value of clock stop number register 40, i.e., before detection of the error, the clock stop indication is given by the output of comparator 60. At the same time, the scan-out is given to the internal state which is preceding the error detection by K-clock.
COPYRIGHT: (C)1980,JPO&Japio
JP524479A 1979-01-19 1979-01-19 Fault record control system Pending JPS5597654A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP524479A JPS5597654A (en) 1979-01-19 1979-01-19 Fault record control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP524479A JPS5597654A (en) 1979-01-19 1979-01-19 Fault record control system

Publications (1)

Publication Number Publication Date
JPS5597654A true JPS5597654A (en) 1980-07-25

Family

ID=11605780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP524479A Pending JPS5597654A (en) 1979-01-19 1979-01-19 Fault record control system

Country Status (1)

Country Link
JP (1) JPS5597654A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05143397A (en) * 1991-11-22 1993-06-11 Nec Corp Status history device
JP2018097559A (en) * 2016-12-13 2018-06-21 Necプラットフォームズ株式会社 Debug circuit and debug test method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05143397A (en) * 1991-11-22 1993-06-11 Nec Corp Status history device
JP2018097559A (en) * 2016-12-13 2018-06-21 Necプラットフォームズ株式会社 Debug circuit and debug test method

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