JPS5596736A - Receiver for broadcast - Google Patents
Receiver for broadcastInfo
- Publication number
- JPS5596736A JPS5596736A JP457879A JP457879A JPS5596736A JP S5596736 A JPS5596736 A JP S5596736A JP 457879 A JP457879 A JP 457879A JP 457879 A JP457879 A JP 457879A JP S5596736 A JPS5596736 A JP S5596736A
- Authority
- JP
- Japan
- Prior art keywords
- output
- clock
- inputted
- receiving
- timer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Circuits Of Receivers In General (AREA)
- Electromechanical Clocks (AREA)
Abstract
PURPOSE:To correct the time automatically only by causing a wall-clock, etc. to approach a receiver for broadcast by providing the transmission function of signals including a time signal at least in the receiver for broadcast with clock and providing a simple receiving function in the wall-clock, etc. CONSTITUTION:The sound part output of receiving part 2 of electronic tuning having antenna 1 is inputted to waveform shaping part 3 also, and the output is connected to timer part 5, the frequency division part of clock part 4 and reset input ends of a part of the time counting part. The time counting part output end of clock part 4 is connected to data selector part 7 and the input end of timer part 5, and the output end of selector part 7 is connected to the signal input end of modulation part 8, and a signal is supplied to the carrier wave input end of modulation part 8 from the frequency division-stage output end of clock part 4. The output of modulation part 8 is connected to transmission element 10 through power amplification part 9. The output of timer part 5 is inputted to control part 6 and the power source control part of receiving part 2, and the output of control part 6 is inputted to the voltage control part of receiving part 2.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4578A JPS5395312A (en) | 1977-01-05 | 1978-01-05 | Pipe coupling and method for forming pipe construction |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5596736A true JPS5596736A (en) | 1980-07-23 |
Family
ID=11463304
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP457879A Pending JPS5596736A (en) | 1978-01-05 | 1979-01-17 | Receiver for broadcast |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5596736A (en) |
-
1979
- 1979-01-17 JP JP457879A patent/JPS5596736A/en active Pending
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