JPS5592957A - Memory access system - Google Patents

Abstract

PURPOSE: To attain efficient memory read operation by providing a buffer circuit to a high-speed memory and low-speed memory respectively and by storing flag data in a high-speed memory buffer during access of the low-speed memory.

CONSTITUTION: Memory 4 is a high-speed memory stored with patterns of alphabets, for example, high in frequency of use, and memory 7 is a low-speed memory stored with character patterns low in frequency of use such as kana characters (Japanese syllabary). Now, when a character to be displayed is an alphabet, its character pattern is read out from high-speed memory 4 at a high speed and then inputted to high-speed memory buffer circuit 5. On the other hand, when it is a kana character, its pattern is inputted to low-speed address register 6 and flag data into which kana character pattern data is inserted is wirtten to the flag bit of circuit 5. Once a low-speed address is detected by the flag bit, a kana character pattern is read out from memory 7 at a low speed and then stored in buffer 8. During this operation, high-speed access to the high-speed memory is attained and both memories are read in parallel, so that efficient memory read operation will be attained.

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