JPS5592084A - Outline signal generation circuit - Google Patents

Outline signal generation circuit

Info

Publication number
JPS5592084A
JPS5592084A JP16336078A JP16336078A JPS5592084A JP S5592084 A JPS5592084 A JP S5592084A JP 16336078 A JP16336078 A JP 16336078A JP 16336078 A JP16336078 A JP 16336078A JP S5592084 A JPS5592084 A JP S5592084A
Authority
JP
Japan
Prior art keywords
noise components
output
level
correction signal
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16336078A
Other languages
Japanese (ja)
Other versions
JPS5919665B2 (en
Inventor
Yasuo Kusano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP53163360A priority Critical patent/JPS5919665B2/en
Publication of JPS5592084A publication Critical patent/JPS5592084A/en
Publication of JPS5919665B2 publication Critical patent/JPS5919665B2/en
Expired legal-status Critical Current

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  • Picture Signal Circuits (AREA)

Abstract

PURPOSE: To improve the SN ratio of an outline correction signal by connecting an amplitude limiting amplifier having a negative feedback circuit to the output terminal which outputs the outline correction signal on a basis of the video signal from a TV camera unit, etc.
CONSTITUTION: An amplitude limiting amplifier having a negative feedback circuit consisting of transistor Q7, resistances R14∼R17, capacitors C2∼C4, and diodes D2 and D3 is connected to output terminal T2. This amplifier has a large gain and a low input impedance in the region of diodes D2 and D3 non-conduction and has a high impedance in the conduction region. Consequently, in respect to the output characteristic for differential inputs of transistors Q3 and Q4, no output appears when they are low-level, and an output appears when they are over a certain input level. As a result, the level of noise components can be made zero by selecting a proper constant as resistance R17 when the video signal including noise components is applied to input terminal T1, so that an outline correction signal of a good SN where noise components are compressed can be obtained from output terminal T2.
COPYRIGHT: (C)1980,JPO&Japio
JP53163360A 1978-12-29 1978-12-29 Contour signal generation circuit Expired JPS5919665B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53163360A JPS5919665B2 (en) 1978-12-29 1978-12-29 Contour signal generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53163360A JPS5919665B2 (en) 1978-12-29 1978-12-29 Contour signal generation circuit

Publications (2)

Publication Number Publication Date
JPS5592084A true JPS5592084A (en) 1980-07-12
JPS5919665B2 JPS5919665B2 (en) 1984-05-08

Family

ID=15772394

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53163360A Expired JPS5919665B2 (en) 1978-12-29 1978-12-29 Contour signal generation circuit

Country Status (1)

Country Link
JP (1) JPS5919665B2 (en)

Also Published As

Publication number Publication date
JPS5919665B2 (en) 1984-05-08

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