JPS5588118A - Buffer read system - Google Patents

Buffer read system

Info

Publication number
JPS5588118A
JPS5588118A JP16228478A JP16228478A JPS5588118A JP S5588118 A JPS5588118 A JP S5588118A JP 16228478 A JP16228478 A JP 16228478A JP 16228478 A JP16228478 A JP 16228478A JP S5588118 A JPS5588118 A JP S5588118A
Authority
JP
Japan
Prior art keywords
information
pointer
buffer
controller
pos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16228478A
Other languages
Japanese (ja)
Inventor
Toshio Katsuki
Michiyuki Kawamura
Masao Kori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16228478A priority Critical patent/JPS5588118A/en
Publication of JPS5588118A publication Critical patent/JPS5588118A/en
Pending legal-status Critical Current

Links

Landscapes

  • Information Transfer Systems (AREA)
  • Computer And Data Communications (AREA)

Abstract

PURPOSE: To remove or reduce a fruitless processing load on a central controller by reading information from a terminal by scanning on a buffer memory at the irreducible minimum of demand.
CONSTITUTION: Information generated by switchboards POS#0...POS#n at rondom is stored in buffer memory BM and coincidence detection circuit C generates an output on detecting a coincidence between addresses that load pointer LP and unload pointer UP indicate respectively. Then, information generating circuit FPG operates by the output of circuit C to generate buffer empty information, and scans sequentially by the scan command of central controller CC from the address which pointer UP indicates to that of memory BM to send the contents back to controller CC, and until controller CC receives the buffer-empty information, scan commands are sent out in sequence. Consequenctly, a fruitless processing load on the unit can be reduced or eliminated.
COPYRIGHT: (C)1980,JPO&Japio
JP16228478A 1978-12-27 1978-12-27 Buffer read system Pending JPS5588118A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16228478A JPS5588118A (en) 1978-12-27 1978-12-27 Buffer read system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16228478A JPS5588118A (en) 1978-12-27 1978-12-27 Buffer read system

Publications (1)

Publication Number Publication Date
JPS5588118A true JPS5588118A (en) 1980-07-03

Family

ID=15751549

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16228478A Pending JPS5588118A (en) 1978-12-27 1978-12-27 Buffer read system

Country Status (1)

Country Link
JP (1) JPS5588118A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60195657A (en) * 1984-03-16 1985-10-04 Hitachi Micro Comput Eng Ltd Data processing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60195657A (en) * 1984-03-16 1985-10-04 Hitachi Micro Comput Eng Ltd Data processing system

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