JPS5580959A - Scanning circuit - Google Patents

Scanning circuit

Info

Publication number
JPS5580959A
JPS5580959A JP15535178A JP15535178A JPS5580959A JP S5580959 A JPS5580959 A JP S5580959A JP 15535178 A JP15535178 A JP 15535178A JP 15535178 A JP15535178 A JP 15535178A JP S5580959 A JPS5580959 A JP S5580959A
Authority
JP
Japan
Prior art keywords
high level
turned
output
mosfet114
node
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15535178A
Other languages
Japanese (ja)
Inventor
Takamichi Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15535178A priority Critical patent/JPS5580959A/en
Publication of JPS5580959A publication Critical patent/JPS5580959A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the power consumption by eliminating the route through which the current flows constantly and at the same time to increase the charging MOSFET regardless of other MOSFET's with forming no inverter within the circuit, thus increasing the scanning speed.
CONSTITUTION: Clear pulse ϕC is applied at t1, and MOSFET115 is turned on to clear the charge of the capacity for MOSFET114 and 118. Then MOSFET113 is turned on at t2 to apply start pulse ϕST to terminal 121, and thus node n1 is set to a high level. The clock ϕ2 is applied in a high level to terminal 120 at t3, and the charging current flows to MOSFET114 to turn scanning output N1 to a high level. And MOSFET117 is also turned on with node n2 set to a high level at t3. Thus output N2 is charged via MOSFET118 to be turned to a high level at t3, and output N1 is set to a low level at the end of t3.
COPYRIGHT: (C)1980,JPO&Japio
JP15535178A 1978-12-15 1978-12-15 Scanning circuit Pending JPS5580959A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15535178A JPS5580959A (en) 1978-12-15 1978-12-15 Scanning circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15535178A JPS5580959A (en) 1978-12-15 1978-12-15 Scanning circuit

Publications (1)

Publication Number Publication Date
JPS5580959A true JPS5580959A (en) 1980-06-18

Family

ID=15603989

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15535178A Pending JPS5580959A (en) 1978-12-15 1978-12-15 Scanning circuit

Country Status (1)

Country Link
JP (1) JPS5580959A (en)

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