JPS5572881A - Correlation processing counter tolerant of multi-echo disturbance - Google Patents

Correlation processing counter tolerant of multi-echo disturbance

Info

Publication number
JPS5572881A
JPS5572881A JP14696478A JP14696478A JPS5572881A JP S5572881 A JPS5572881 A JP S5572881A JP 14696478 A JP14696478 A JP 14696478A JP 14696478 A JP14696478 A JP 14696478A JP S5572881 A JPS5572881 A JP S5572881A
Authority
JP
Japan
Prior art keywords
code
output
correlation processing
tolerant
echo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14696478A
Other languages
Japanese (ja)
Inventor
Yukio Kobayashi
Nobuyuki Tokura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP14696478A priority Critical patent/JPS5572881A/en
Publication of JPS5572881A publication Critical patent/JPS5572881A/en
Pending legal-status Critical Current

Links

Landscapes

  • Radar Systems Or Details Thereof (AREA)
  • Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)

Abstract

PURPOSE: To obtain a correlation processing counter tolerant of multi-echo disturbance, by providing a 2nd code generator which generate a ternal signal of a positive, negative or zero level.
CONSTITUTION: In 1st code generator 11, false random code generator 13 generates a false random code synchronizing with pulses from clock pulse generator 12, and this code and clock pulses are exclusively OR-ed 14. Its output C is sent to a transmission line to be measured through modulation part 15. Output C, on the other hand, is branched and then inputted to 2nd code generating part 21 by way of delay circuit 19. Next, logic circuit 23 in generating part 21 adds output C to the output of unit clock delay circuit 22, thereby generating a ternary signal of a positive, negative and zero level. In correlation processing part 24, an arrival signal from measured transmission line 18 is correleated with the output code of 2nd code generating part 21. In this way, a correlation processing measuring unit can be obtained which is tolerant of multi-echo disturbance.
COPYRIGHT: (C)1980,JPO&Japio
JP14696478A 1978-11-27 1978-11-27 Correlation processing counter tolerant of multi-echo disturbance Pending JPS5572881A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14696478A JPS5572881A (en) 1978-11-27 1978-11-27 Correlation processing counter tolerant of multi-echo disturbance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14696478A JPS5572881A (en) 1978-11-27 1978-11-27 Correlation processing counter tolerant of multi-echo disturbance

Publications (1)

Publication Number Publication Date
JPS5572881A true JPS5572881A (en) 1980-06-02

Family

ID=15419556

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14696478A Pending JPS5572881A (en) 1978-11-27 1978-11-27 Correlation processing counter tolerant of multi-echo disturbance

Country Status (1)

Country Link
JP (1) JPS5572881A (en)

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