JPS5569841A - Expansion and contraction system for character pattern - Google Patents

Expansion and contraction system for character pattern

Info

Publication number
JPS5569841A
JPS5569841A JP14194978A JP14194978A JPS5569841A JP S5569841 A JPS5569841 A JP S5569841A JP 14194978 A JP14194978 A JP 14194978A JP 14194978 A JP14194978 A JP 14194978A JP S5569841 A JPS5569841 A JP S5569841A
Authority
JP
Japan
Prior art keywords
pattern
character pattern
additional information
row
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14194978A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Michi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14194978A priority Critical patent/JPS5569841A/en
Publication of JPS5569841A publication Critical patent/JPS5569841A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To convert a character pattern by composing a row and column converter circuit part of various kinds of row and column logic circuits, by presetting additional information equivalent to the character pattern and then by selecting a logic circuit by this additional information.
CONSTITUTION: Additional information equivalent to character pattern 4 of MO rows by NO columns is stored 8 and 9 being preset to each pattern in a desired form. An assigned row logic circuit is selected from several ones constituting respective row converter circuit part 7, and unit additional information set in each unit memory area of memory circuit 8 is row-converted into character pattern 5 of Mi rows by NO columns. Next, pattern 5 is converted into a pattern of NO by Ni by a column logic circuit similarly selected by using unit additional information set in each unit memory area of memory circuit 9 to obtain character pattern 6 of Mi by Ni. This constitution provides the excellent and fast conversion of respective character patterns.
COPYRIGHT: (C)1980,JPO&Japio
JP14194978A 1978-11-17 1978-11-17 Expansion and contraction system for character pattern Pending JPS5569841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14194978A JPS5569841A (en) 1978-11-17 1978-11-17 Expansion and contraction system for character pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14194978A JPS5569841A (en) 1978-11-17 1978-11-17 Expansion and contraction system for character pattern

Publications (1)

Publication Number Publication Date
JPS5569841A true JPS5569841A (en) 1980-05-26

Family

ID=15303871

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14194978A Pending JPS5569841A (en) 1978-11-17 1978-11-17 Expansion and contraction system for character pattern

Country Status (1)

Country Link
JP (1) JPS5569841A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6086588A (en) * 1983-10-18 1985-05-16 富士通株式会社 Character pattern generator
JPS6180954A (en) * 1984-09-28 1986-04-24 Nec Corp Reducing system of dot pattern character

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6086588A (en) * 1983-10-18 1985-05-16 富士通株式会社 Character pattern generator
JPH0226234B2 (en) * 1983-10-18 1990-06-08 Fujitsu Ltd
JPS6180954A (en) * 1984-09-28 1986-04-24 Nec Corp Reducing system of dot pattern character

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