JPS5567988A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS5567988A
JPS5567988A JP13980178A JP13980178A JPS5567988A JP S5567988 A JPS5567988 A JP S5567988A JP 13980178 A JP13980178 A JP 13980178A JP 13980178 A JP13980178 A JP 13980178A JP S5567988 A JPS5567988 A JP S5567988A
Authority
JP
Japan
Prior art keywords
data
front half
counter
transfer
latter half
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13980178A
Other languages
Japanese (ja)
Inventor
Kiyohiko Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP13980178A priority Critical patent/JPS5567988A/en
Publication of JPS5567988A publication Critical patent/JPS5567988A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To realize high-speed transfer of data to RAM by writing the latter half of data in RAM except its front half when the front half and latter half of transfer data are separated in a cyclic shift register.
CONSTITUTION: In accordance with count address (b), initial address (a) and data bit length (l) of counter A, register B and counter C, arithmetic processing circuit PV makes a decision on whether the relation shown by formula I is satisfied or not and when it is satisfied, it is judged that transfer data is divided into front half (d1) and latter half (d2) in cyclic shift register SR. Then circuit PV re-sets the bit length of counter C to bit length (l2) calculated by l2=l-(a-b). Consequently, latter half (d2) is written in RAM except the front half part of an accessed part without waiting appearance of the initial address of front half part (d1) at read terminal R of register SR, thereby realising high-speed data transfer.
COPYRIGHT: (C)1980,JPO&Japio
JP13980178A 1978-11-15 1978-11-15 Data transfer system Pending JPS5567988A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13980178A JPS5567988A (en) 1978-11-15 1978-11-15 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13980178A JPS5567988A (en) 1978-11-15 1978-11-15 Data transfer system

Publications (1)

Publication Number Publication Date
JPS5567988A true JPS5567988A (en) 1980-05-22

Family

ID=15253740

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13980178A Pending JPS5567988A (en) 1978-11-15 1978-11-15 Data transfer system

Country Status (1)

Country Link
JP (1) JPS5567988A (en)

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