JPS556688A - Binary level decision circuit - Google Patents

Binary level decision circuit

Info

Publication number
JPS556688A
JPS556688A JP7962778A JP7962778A JPS556688A JP S556688 A JPS556688 A JP S556688A JP 7962778 A JP7962778 A JP 7962778A JP 7962778 A JP7962778 A JP 7962778A JP S556688 A JPS556688 A JP S556688A
Authority
JP
Japan
Prior art keywords
circuit
brightness
level
distribution
analytic signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7962778A
Other languages
Japanese (ja)
Inventor
Takeshi Inoue
Masahiro Nagao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7962778A priority Critical patent/JPS556688A/en
Publication of JPS556688A publication Critical patent/JPS556688A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To make it possible to determine an optimum threshold level with remarkably high accuracy by counting a sample group with specific relation according to lightness levels and using the brightness distribution of shape features for the determination of the optimum threshold level.
CONSTITUTION: Feature extraction circuit 6 is given a level pattern obtained from one shape feature of the observation object of TV camera 1 by expressing by electric levels. By sampling the output of comparator circuit 2, circuit 6 extracts and sends the n -number samples to counter circuit 7 when the n -number samples or more of level 1 continues. The discrete values of counter circuits 3 and 7 are inputted to analyzer circuit 8. Circuit 8 supplies brightness analytic signal (b0) to D/A converter circuit 4. Further, circuit 8 calculates the distribution to the brightness analytic signal (b) of the difference of the discrete value of circuit 3 and the distribution to the brightness analytic signal level of the difference of the discrete value of circuit 7. Then, analyzer circuit 8 regards a brightness level, equivalent to the specific point of the discrete value of circuit 7, as the best threshold level and sends it out.
COPYRIGHT: (C)1980,JPO&Japio
JP7962778A 1978-06-29 1978-06-29 Binary level decision circuit Pending JPS556688A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7962778A JPS556688A (en) 1978-06-29 1978-06-29 Binary level decision circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7962778A JPS556688A (en) 1978-06-29 1978-06-29 Binary level decision circuit

Publications (1)

Publication Number Publication Date
JPS556688A true JPS556688A (en) 1980-01-18

Family

ID=13695306

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7962778A Pending JPS556688A (en) 1978-06-29 1978-06-29 Binary level decision circuit

Country Status (1)

Country Link
JP (1) JPS556688A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5999584A (en) * 1982-11-30 1984-06-08 Toshiba Corp Determining device of optimum binary reference voltage
JPS59184803A (en) * 1983-04-06 1984-10-20 Mitsubishi Chem Ind Ltd Processing system of high-speed image processor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5999584A (en) * 1982-11-30 1984-06-08 Toshiba Corp Determining device of optimum binary reference voltage
JPS59184803A (en) * 1983-04-06 1984-10-20 Mitsubishi Chem Ind Ltd Processing system of high-speed image processor

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