JPS556655A - Detection and processing system for fault - Google Patents

Detection and processing system for fault

Info

Publication number
JPS556655A
JPS556655A JP7940678A JP7940678A JPS556655A JP S556655 A JPS556655 A JP S556655A JP 7940678 A JP7940678 A JP 7940678A JP 7940678 A JP7940678 A JP 7940678A JP S556655 A JPS556655 A JP S556655A
Authority
JP
Japan
Prior art keywords
unit
sub units
signal
common bus
units
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7940678A
Other languages
Japanese (ja)
Inventor
Takashi Ishikawa
Akira Onodera
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7940678A priority Critical patent/JPS556655A/en
Publication of JPS556655A publication Critical patent/JPS556655A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To send out a blocking indication signal, which stops the transmission of signals from all of units connected to a common bus to signal lines, from a main unit by coupling several main units with sub units via signal lines made into the common bus, and also to detect the existence of a fault signal during the transmission of this signal.
CONSTITUTION: Center processor MD is connected to sub units SD1 to SD4 via common bus CB, and between processor MD and sub units SD1 to SD4, signals are transmitted and received via common bus CB. Then, blocking signal lines SG1 to SG4 are provided which send out blocking indication signal B together with interface signals to be transmitted from unit MD to respective sub units SD1 to SD4. this blocking indication signal B is transmitted from unit MD to all sub units SD1 to SD4 while the sending of signals from unit DM and all sub units SD1 to SD4 to common bus CB is stopped, and the fault detector provided to unit MD or supervisory unit W makes a check on the existence of a fault signal as to unit MD and all sub units SD1 to SD4.
COPYRIGHT: (C)1980,JPO&Japio
JP7940678A 1978-06-30 1978-06-30 Detection and processing system for fault Pending JPS556655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7940678A JPS556655A (en) 1978-06-30 1978-06-30 Detection and processing system for fault

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7940678A JPS556655A (en) 1978-06-30 1978-06-30 Detection and processing system for fault

Publications (1)

Publication Number Publication Date
JPS556655A true JPS556655A (en) 1980-01-18

Family

ID=13688966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7940678A Pending JPS556655A (en) 1978-06-30 1978-06-30 Detection and processing system for fault

Country Status (1)

Country Link
JP (1) JPS556655A (en)

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