JPS5566143A - Programmable divider - Google Patents
Programmable dividerInfo
- Publication number
- JPS5566143A JPS5566143A JP14018978A JP14018978A JPS5566143A JP S5566143 A JPS5566143 A JP S5566143A JP 14018978 A JP14018978 A JP 14018978A JP 14018978 A JP14018978 A JP 14018978A JP S5566143 A JPS5566143 A JP S5566143A
- Authority
- JP
- Japan
- Prior art keywords
- contents
- specified
- counter
- division ratio
- specified constant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 abstract 3
- 238000006243 chemical reaction Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Superheterodyne Receivers (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14018978A JPS5566143A (en) | 1978-11-13 | 1978-11-13 | Programmable divider |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14018978A JPS5566143A (en) | 1978-11-13 | 1978-11-13 | Programmable divider |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5566143A true JPS5566143A (en) | 1980-05-19 |
JPS6126B2 JPS6126B2 (ja) | 1986-01-06 |
Family
ID=15262970
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14018978A Granted JPS5566143A (en) | 1978-11-13 | 1978-11-13 | Programmable divider |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5566143A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19700017A1 (de) * | 1996-01-29 | 1997-08-07 | Fujitsu Ltd | Swallowzähler mit Modulsignalausgabesteuerung |
-
1978
- 1978-11-13 JP JP14018978A patent/JPS5566143A/ja active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19700017A1 (de) * | 1996-01-29 | 1997-08-07 | Fujitsu Ltd | Swallowzähler mit Modulsignalausgabesteuerung |
DE19700017C2 (de) * | 1996-01-29 | 1998-04-09 | Fujitsu Ltd | Swallowzähler mit Modulsignalausgabesteuerung, sowie Vergleichsfrequenzteiler und PLL-Freuqenz-Synthesizerschaltung |
US5878101A (en) * | 1996-01-29 | 1999-03-02 | Fujitsu Limited | Swallow counter with modulus signal output control |
US5982840A (en) * | 1996-01-29 | 1999-11-09 | Fujitsu Limited | Swallow counter with modulus signal output control |
Also Published As
Publication number | Publication date |
---|---|
JPS6126B2 (ja) | 1986-01-06 |
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