JPS5563418A - Option connecting system - Google Patents

Option connecting system

Info

Publication number
JPS5563418A
JPS5563418A JP13647278A JP13647278A JPS5563418A JP S5563418 A JPS5563418 A JP S5563418A JP 13647278 A JP13647278 A JP 13647278A JP 13647278 A JP13647278 A JP 13647278A JP S5563418 A JPS5563418 A JP S5563418A
Authority
JP
Japan
Prior art keywords
instruction
error
busy
signal
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13647278A
Other languages
Japanese (ja)
Other versions
JPS602705B2 (en
Inventor
Shinji Nishibe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP53136472A priority Critical patent/JPS602705B2/en
Publication of JPS5563418A publication Critical patent/JPS5563418A/en
Publication of JPS602705B2 publication Critical patent/JPS602705B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Advance Control (AREA)

Abstract

PURPOSE: To reduce the number of lines for interface, by connecting a plurality of operating options to CPU to judge the self processing of instruction code from CPU, and by producing the production of busy signal when required.
CONSTITUTION: The designation instruction of the operating option operation transferred from CPU to the operating options 11 and 12 decodes whether it is the instruction to itself or not. If the instruction is to itself, the busy instruction is caused and the signal is transferred to the busy bus 14. At the occurrence of busy signal, when error is set with FF11B, 12B set based on the result of check for the presence of error of the options 11 and 12 themselves, error signal is transferred to the error bus 15.
COPYRIGHT: (C)1980,JPO&Japio
JP53136472A 1978-11-06 1978-11-06 Optional connection method Expired JPS602705B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53136472A JPS602705B2 (en) 1978-11-06 1978-11-06 Optional connection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53136472A JPS602705B2 (en) 1978-11-06 1978-11-06 Optional connection method

Publications (2)

Publication Number Publication Date
JPS5563418A true JPS5563418A (en) 1980-05-13
JPS602705B2 JPS602705B2 (en) 1985-01-23

Family

ID=15175910

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53136472A Expired JPS602705B2 (en) 1978-11-06 1978-11-06 Optional connection method

Country Status (1)

Country Link
JP (1) JPS602705B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60142743A (en) * 1983-12-29 1985-07-27 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Internal bus system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60142743A (en) * 1983-12-29 1985-07-27 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Internal bus system
JPH0135367B2 (en) * 1983-12-29 1989-07-25 Intaanashonaru Bijinesu Mashiinzu Corp

Also Published As

Publication number Publication date
JPS602705B2 (en) 1985-01-23

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