JPS5559555A - High-speed level switching device - Google Patents

High-speed level switching device

Info

Publication number
JPS5559555A
JPS5559555A JP13218478A JP13218478A JPS5559555A JP S5559555 A JPS5559555 A JP S5559555A JP 13218478 A JP13218478 A JP 13218478A JP 13218478 A JP13218478 A JP 13218478A JP S5559555 A JPS5559555 A JP S5559555A
Authority
JP
Japan
Prior art keywords
interruption
level
register set
stored
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13218478A
Other languages
Japanese (ja)
Other versions
JPS6148743B2 (en
Inventor
Hiroshi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13218478A priority Critical patent/JPS5559555A/en
Publication of JPS5559555A publication Critical patent/JPS5559555A/en
Publication of JPS6148743B2 publication Critical patent/JPS6148743B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To decrease the overhead occuring at the level switching time by installing the main memory means possessing the interruption shunt regions of the prescribed number plus the plural interrruption level information storing means in a smaller number then that of the shunt regions.
CONSTITUTION: At the initial state, the initial value of interruption level register set selection register 4 is decoded by decoder 5 and then selected as the register set using 1st interruption level register 2 with the program of level l0 under running. When the request of interruption level l1 is given at time t0, the higher rank than level l0 is detected at priority interruption decision circuit 12 to accept the interruption. Regsister 4 selects unused register set 3, and the information in read from interruption shunt region 9 of main memory 7 for the program running at level l1 to be stored within set 3. When the unused register set is not available, the interruption level information stored in the oldest time is stored in the shunt region of memory 7. And then the interruption level information is stored in the register set.
COPYRIGHT: (C)1980,JPO&Japio
JP13218478A 1978-10-27 1978-10-27 High-speed level switching device Granted JPS5559555A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13218478A JPS5559555A (en) 1978-10-27 1978-10-27 High-speed level switching device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13218478A JPS5559555A (en) 1978-10-27 1978-10-27 High-speed level switching device

Publications (2)

Publication Number Publication Date
JPS5559555A true JPS5559555A (en) 1980-05-06
JPS6148743B2 JPS6148743B2 (en) 1986-10-25

Family

ID=15075344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13218478A Granted JPS5559555A (en) 1978-10-27 1978-10-27 High-speed level switching device

Country Status (1)

Country Link
JP (1) JPS5559555A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57161934A (en) * 1981-03-30 1982-10-05 Fujitsu Ltd Microprogram controlling system
JPS5814253A (en) * 1981-07-17 1983-01-27 Nec Corp Interruption system for central processor
JPS62267835A (en) * 1986-05-15 1987-11-20 Fujitsu Ltd Control system for allocation of physical block
JPS6352240A (en) * 1986-08-22 1988-03-05 Hitachi Ltd Data processor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4966041A (en) * 1972-10-27 1974-06-26

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4966041A (en) * 1972-10-27 1974-06-26

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57161934A (en) * 1981-03-30 1982-10-05 Fujitsu Ltd Microprogram controlling system
JPH0115094B2 (en) * 1981-03-30 1989-03-15 Fujitsu Ltd
JPS5814253A (en) * 1981-07-17 1983-01-27 Nec Corp Interruption system for central processor
JPS62267835A (en) * 1986-05-15 1987-11-20 Fujitsu Ltd Control system for allocation of physical block
JPS6352240A (en) * 1986-08-22 1988-03-05 Hitachi Ltd Data processor

Also Published As

Publication number Publication date
JPS6148743B2 (en) 1986-10-25

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