JPS5553740A - Velocity converting circuit between central processor and terminal unit - Google Patents
Velocity converting circuit between central processor and terminal unitInfo
- Publication number
- JPS5553740A JPS5553740A JP12716478A JP12716478A JPS5553740A JP S5553740 A JPS5553740 A JP S5553740A JP 12716478 A JP12716478 A JP 12716478A JP 12716478 A JP12716478 A JP 12716478A JP S5553740 A JPS5553740 A JP S5553740A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- data
- terminal unit
- velocity
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Information Transfer Systems (AREA)
- Communication Control (AREA)
Abstract
PURPOSE: To obtain a velocity conversion circuit which can perform the data process via the terminal unit which is nonsynchronous with the CPU by using the FIFO memory circuit and thus setting the writing velocity and the reading velocity independently from each other.
CONSTITUTION: Transfer request signal 320 is generated from data transfer request generation circuit 304 in velocity converting circuit 302 via ready signal 314 sent from terminal unit 303 corresponding to data transfer start signal 313 sent from CPU301. Thus clock signal 321 from the CPU is received at clock signal generation circuit 305, and clock 325 of the necessary cycle at terminal 303 is generated. Both signal 321 and N-word data signal 322 are received at FIFO memory 307, and data signal 326 is sent to the terminal unit after converting into the cycle speed of signal 325. At the same time, memory word number W set previously to register 324 and output 329 of counter 306 are subtracted at subtractor circuit 308, and then value M obtained the subtraction is compared with designation signal 323 of the block length N at comparator 310. Thus in the case of N M, new transfer request signal 320 is generated to transfer the next block data through the CPU.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12716478A JPS5553740A (en) | 1978-10-16 | 1978-10-16 | Velocity converting circuit between central processor and terminal unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12716478A JPS5553740A (en) | 1978-10-16 | 1978-10-16 | Velocity converting circuit between central processor and terminal unit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5553740A true JPS5553740A (en) | 1980-04-19 |
JPS618967B2 JPS618967B2 (en) | 1986-03-19 |
Family
ID=14953224
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12716478A Granted JPS5553740A (en) | 1978-10-16 | 1978-10-16 | Velocity converting circuit between central processor and terminal unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5553740A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6059432A (en) * | 1983-09-10 | 1985-04-05 | Fujitsu Ltd | Data buffer control method of input and output device |
JPS6325722A (en) * | 1986-07-18 | 1988-02-03 | Matsushita Electric Ind Co Ltd | Fifo circuit |
WO2000064161A1 (en) * | 1999-04-16 | 2000-10-26 | Sony Corporation | Method and device for data transmission |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0334855Y2 (en) * | 1986-11-13 | 1991-07-24 | ||
US4734057A (en) * | 1987-03-02 | 1988-03-29 | Burndy Corporation | Connector assembly |
JPH01121273U (en) * | 1988-02-09 | 1989-08-17 |
-
1978
- 1978-10-16 JP JP12716478A patent/JPS5553740A/en active Granted
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6059432A (en) * | 1983-09-10 | 1985-04-05 | Fujitsu Ltd | Data buffer control method of input and output device |
JPH0410652B2 (en) * | 1983-09-10 | 1992-02-26 | ||
JPS6325722A (en) * | 1986-07-18 | 1988-02-03 | Matsushita Electric Ind Co Ltd | Fifo circuit |
WO2000064161A1 (en) * | 1999-04-16 | 2000-10-26 | Sony Corporation | Method and device for data transmission |
US7012964B1 (en) | 1999-04-16 | 2006-03-14 | Sony Corporation | Method and device for data transmission |
Also Published As
Publication number | Publication date |
---|---|
JPS618967B2 (en) | 1986-03-19 |
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