JPS5553740A - Velocity converting circuit between central processor and terminal unit - Google Patents

Abstract

PURPOSE: To obtain a velocity conversion circuit which can perform the data process via the terminal unit which is nonsynchronous with the CPU by using the FIFO memory circuit and thus setting the writing velocity and the reading velocity independently from each other.

CONSTITUTION: Transfer request signal 320 is generated from data transfer request generation circuit 304 in velocity converting circuit 302 via ready signal 314 sent from terminal unit 303 corresponding to data transfer start signal 313 sent from CPU301. Thus clock signal 321 from the CPU is received at clock signal generation circuit 305, and clock 325 of the necessary cycle at terminal 303 is generated. Both signal 321 and N-word data signal 322 are received at FIFO memory 307, and data signal 326 is sent to the terminal unit after converting into the cycle speed of signal 325. At the same time, memory word number W set previously to register 324 and output 329 of counter 306 are subtracted at subtractor circuit 308, and then value M obtained the subtraction is compared with designation signal 323 of the block length N at comparator 310. Thus in the case of N M, new transfer request signal 320 is generated to transfer the next block data through the CPU.

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