JPS5552542A - Recording and reproducting circuit - Google Patents

Recording and reproducting circuit

Info

Publication number
JPS5552542A
JPS5552542A JP12384678A JP12384678A JPS5552542A JP S5552542 A JPS5552542 A JP S5552542A JP 12384678 A JP12384678 A JP 12384678A JP 12384678 A JP12384678 A JP 12384678A JP S5552542 A JPS5552542 A JP S5552542A
Authority
JP
Japan
Prior art keywords
circuit
control signal
signal
terminal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12384678A
Other languages
Japanese (ja)
Inventor
Masami Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP12384678A priority Critical patent/JPS5552542A/en
Publication of JPS5552542A publication Critical patent/JPS5552542A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent sound quality from lowering and also to dectct a control signal definitely, by providing a method of detecting only a control signal frequency component in reproduction and that which does not detect the same component and by omitting HPF.
CONSTITUTION: The record a control signal, switch S4 is connected to side (a) and the control signal from control signal oscillation circuit 4 is recorded through terminal R.HEAD. In this case, the recording of a sound signal is interruped. In reproduction, a signal detected by terminal P.HEAD is amplified by pre-amplifier 1 and branched. The 1st signal is amplified by main amplifier 3 to obtain a sound signal from terminal S.P. The 2nd one is inputted to integrating circuit 6 through BPF5. The 3rd one is inputted to integrating circuit 8 after its control signal frequency component is removed by tape circuit 7. Output C of circuit 8 is inverted by inverter 9 to obtain signal D, which is applied to AND gate 10 together with output B of circuit 6, thereby obtaining output E.
COPYRIGHT: (C)1980,JPO&Japio
JP12384678A 1978-10-05 1978-10-05 Recording and reproducting circuit Pending JPS5552542A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12384678A JPS5552542A (en) 1978-10-05 1978-10-05 Recording and reproducting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12384678A JPS5552542A (en) 1978-10-05 1978-10-05 Recording and reproducting circuit

Publications (1)

Publication Number Publication Date
JPS5552542A true JPS5552542A (en) 1980-04-17

Family

ID=14870832

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12384678A Pending JPS5552542A (en) 1978-10-05 1978-10-05 Recording and reproducting circuit

Country Status (1)

Country Link
JP (1) JPS5552542A (en)

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