JPS5552169A - Multiplex processor system - Google Patents

Multiplex processor system

Info

Publication number
JPS5552169A
JPS5552169A JP12554978A JP12554978A JPS5552169A JP S5552169 A JPS5552169 A JP S5552169A JP 12554978 A JP12554978 A JP 12554978A JP 12554978 A JP12554978 A JP 12554978A JP S5552169 A JPS5552169 A JP S5552169A
Authority
JP
Japan
Prior art keywords
timer
circuit
processing unit
sets
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12554978A
Other languages
Japanese (ja)
Other versions
JPS6118793B2 (en
Inventor
Saburo Otaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12554978A priority Critical patent/JPS5552169A/en
Publication of JPS5552169A publication Critical patent/JPS5552169A/en
Publication of JPS6118793B2 publication Critical patent/JPS6118793B2/ja
Granted legal-status Critical Current

Links

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  • Hardware Redundancy (AREA)

Abstract

PURPOSE: To perform the readout of count value of timer in high speed by keeping the synchronism of timer in the system, through the provision of output processing circuit of timer.
CONSTITUTION: When the processing unit 1 stores new timer value to the timer circuit 12, the timer control circuit 10 sets the timer renewal suppression FF, and this output is given to the timer circuit via the OR gate 22 to stop the renewal of timer. Further, the output of FF21 is fed to other processing unit 2 ans similar operation is made. Next, the circuit 10 sets the timer set value to the communication register 20 and after that, sets it to the timer circuit 12 via the data line 201. Further, when the start of the communication between processing units is requested to the communication control circuit 11 via the signal line 106, the circuit 11 delivers request signal via the control line 108 to other processing unit 2 and delivers the timer set data to the processing unit 2 via the data line 201.
COPYRIGHT: (C)1980,JPO&Japio
JP12554978A 1978-10-11 1978-10-11 Multiplex processor system Granted JPS5552169A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12554978A JPS5552169A (en) 1978-10-11 1978-10-11 Multiplex processor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12554978A JPS5552169A (en) 1978-10-11 1978-10-11 Multiplex processor system

Publications (2)

Publication Number Publication Date
JPS5552169A true JPS5552169A (en) 1980-04-16
JPS6118793B2 JPS6118793B2 (en) 1986-05-14

Family

ID=14912944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12554978A Granted JPS5552169A (en) 1978-10-11 1978-10-11 Multiplex processor system

Country Status (1)

Country Link
JP (1) JPS5552169A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57155648A (en) * 1981-03-20 1982-09-25 Fujitsu Ltd Diagnosing system of stand-by group information processor
JPS62204365A (en) * 1986-03-04 1987-09-09 Nec Corp Information processing system
WO2014068774A1 (en) * 2012-11-02 2014-05-08 富士通株式会社 Information processing device, arithmetic processing device, and counter synchronization method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57155648A (en) * 1981-03-20 1982-09-25 Fujitsu Ltd Diagnosing system of stand-by group information processor
JPS6246020B2 (en) * 1981-03-20 1987-09-30 Fujitsu Ltd
JPS62204365A (en) * 1986-03-04 1987-09-09 Nec Corp Information processing system
WO2014068774A1 (en) * 2012-11-02 2014-05-08 富士通株式会社 Information processing device, arithmetic processing device, and counter synchronization method

Also Published As

Publication number Publication date
JPS6118793B2 (en) 1986-05-14

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