JPS5552129A - Data processing control system - Google Patents

Data processing control system

Info

Publication number
JPS5552129A
JPS5552129A JP12425578A JP12425578A JPS5552129A JP S5552129 A JPS5552129 A JP S5552129A JP 12425578 A JP12425578 A JP 12425578A JP 12425578 A JP12425578 A JP 12425578A JP S5552129 A JPS5552129 A JP S5552129A
Authority
JP
Japan
Prior art keywords
processing
firm ware
data processing
interruption signal
interruption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12425578A
Other languages
Japanese (ja)
Inventor
Nobuhiko Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12425578A priority Critical patent/JPS5552129A/en
Publication of JPS5552129A publication Critical patent/JPS5552129A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To quicken the firm ware processing, by classifying the content of processing and informing the start of processing to the firm ware control block with respective interruption signal.
CONSTITUTION: The data processing request is inputted to the reception sections 104 and 105 from CPU. The decoder 107 decodes the data and feeds it to one of the interruption signal generation sections 108 and 110. The start signal from the reception section 104 is also fed to one of the generation sections 108W110. The generation section receiving the both signals delivers the interruption signal to the interruption managing section 11 and moves control to suitable routine in the firm ware program. Since the classification of the content of processing is made at the time when the input and output request is fed, the processing time required in the firm ware control block 103 can be reduced.
COPYRIGHT: (C)1980,JPO&Japio
JP12425578A 1978-10-09 1978-10-09 Data processing control system Pending JPS5552129A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12425578A JPS5552129A (en) 1978-10-09 1978-10-09 Data processing control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12425578A JPS5552129A (en) 1978-10-09 1978-10-09 Data processing control system

Publications (1)

Publication Number Publication Date
JPS5552129A true JPS5552129A (en) 1980-04-16

Family

ID=14880794

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12425578A Pending JPS5552129A (en) 1978-10-09 1978-10-09 Data processing control system

Country Status (1)

Country Link
JP (1) JPS5552129A (en)

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