JPS5545249A - Differential non-linearity correction system of analogue digital converter - Google Patents

Differential non-linearity correction system of analogue digital converter

Info

Publication number
JPS5545249A
JPS5545249A JP11837978A JP11837978A JPS5545249A JP S5545249 A JPS5545249 A JP S5545249A JP 11837978 A JP11837978 A JP 11837978A JP 11837978 A JP11837978 A JP 11837978A JP S5545249 A JPS5545249 A JP S5545249A
Authority
JP
Japan
Prior art keywords
lower limit
signals
converter
width
linearity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11837978A
Other languages
Japanese (ja)
Other versions
JPS5930343B2 (en
Inventor
Atsushi Yoshimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
METSUKU KK
Original Assignee
METSUKU KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by METSUKU KK filed Critical METSUKU KK
Priority to JP11837978A priority Critical patent/JPS5930343B2/en
Publication of JPS5545249A publication Critical patent/JPS5545249A/en
Publication of JPS5930343B2 publication Critical patent/JPS5930343B2/en
Expired legal-status Critical Current

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Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: To make it possible to correct the differential non-linearity of an A/D converter in real time by dividing the error between each output channel CH width of the A/D converter and the correct width into upper and lower limit values and storing them in the ROM for every CH.
CONSTITUTION: When analogue signals are inputted to A/D converter 1, digital signals are outputted, and upper and lower limit values are read out from ROM 2 where the error between the CH width of the CH number corresponding to this output and the correct width is divided into upper and lower limit values and is stored. Upper and lower limit values are inputted to digital comparator 4 for the upper limit value and digital comparator 5 for the lower limit value respectively. Meanwhile, random binary generator 3 gives always random signals to comparators and compares two signals just when read signals from ROM 2 are inputted to comparators and gives a 1 addition or subtraction command to operator 6 on a basis of outputs of comparators 4 and 5 when the random value is larger or smaller than the upper limit and the lower limit. As a result, the differential non-linearity of the high-speed A/D converter can be corrected in real time to obtain good-differential linearity data.
COPYRIGHT: (C)1980,JPO&Japio
JP11837978A 1978-09-26 1978-09-26 Differential nonlinearity correction method for analog-to-digital converters Expired JPS5930343B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11837978A JPS5930343B2 (en) 1978-09-26 1978-09-26 Differential nonlinearity correction method for analog-to-digital converters

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11837978A JPS5930343B2 (en) 1978-09-26 1978-09-26 Differential nonlinearity correction method for analog-to-digital converters

Publications (2)

Publication Number Publication Date
JPS5545249A true JPS5545249A (en) 1980-03-29
JPS5930343B2 JPS5930343B2 (en) 1984-07-26

Family

ID=14735234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11837978A Expired JPS5930343B2 (en) 1978-09-26 1978-09-26 Differential nonlinearity correction method for analog-to-digital converters

Country Status (1)

Country Link
JP (1) JPS5930343B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61294505A (en) * 1985-06-24 1986-12-25 Nippon Denso Co Ltd Digital arithmetic unit for vehicle control system
JPS62118845A (en) * 1985-11-20 1987-05-30 Meiji Milk Prod Co Ltd Continuous whipping device
JPS62126936A (en) * 1985-10-17 1987-06-09 ブレビル ア−ル アンド デイ− プロプライエタリイ リミテツド Household ice cream maker
US4800574A (en) * 1983-05-10 1989-01-24 Ricoh Company, Ltd. Digital modulator/demodulator including non-linear analog-to-digital converter and circuitry compensating for the non-linearity of the converter

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4800574A (en) * 1983-05-10 1989-01-24 Ricoh Company, Ltd. Digital modulator/demodulator including non-linear analog-to-digital converter and circuitry compensating for the non-linearity of the converter
JPS61294505A (en) * 1985-06-24 1986-12-25 Nippon Denso Co Ltd Digital arithmetic unit for vehicle control system
JPS62126936A (en) * 1985-10-17 1987-06-09 ブレビル ア−ル アンド デイ− プロプライエタリイ リミテツド Household ice cream maker
JPH0151982B2 (en) * 1985-10-17 1989-11-07 Breville Holdings Pty Ltd
JPS62118845A (en) * 1985-11-20 1987-05-30 Meiji Milk Prod Co Ltd Continuous whipping device
JPH0156737B2 (en) * 1985-11-20 1989-12-01 Meiji Milk Prod Co Ltd

Also Published As

Publication number Publication date
JPS5930343B2 (en) 1984-07-26

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