JPS5542441A - Test system for time-division channel - Google Patents

Test system for time-division channel

Info

Publication number
JPS5542441A
JPS5542441A JP11575778A JP11575778A JPS5542441A JP S5542441 A JPS5542441 A JP S5542441A JP 11575778 A JP11575778 A JP 11575778A JP 11575778 A JP11575778 A JP 11575778A JP S5542441 A JPS5542441 A JP S5542441A
Authority
JP
Japan
Prior art keywords
parity
time
module
division channel
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11575778A
Other languages
Japanese (ja)
Inventor
Akira Horiki
Kazuo Hamasato
Kiyotaka Kameda
Akira Kawada
Yuzo Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP11575778A priority Critical patent/JPS5542441A/en
Publication of JPS5542441A publication Critical patent/JPS5542441A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/22—Arrangements for supervision, monitoring or testing
    • H04M3/24—Arrangements for supervision, monitoring or testing with provision for checking the normal operation
    • H04M3/244—Arrangements for supervision, monitoring or testing with provision for checking the normal operation for multiplex systems

Abstract

PURPOSE:To enhance the reliability through the facilitated switching to the auxiliary module by dividing the time-division channel into many sections and then providing the parity arithmetic circuit featuring the check and generating functions of the parity at each node between the divided sections. CONSTITUTION:Time-division channel modules 1-N are connected to junctor highways j11...j1N...JN1...JNN, and parity arithmetic circuit 12 is added at the reception side of these junction highways, Then the parity bit is applied through parity generator 10 connected to highway, i, and the data is sent to module N via multiplexer 2 and highway j1N. Thus the parity bit is generated from the bit code received at circuit 12 of module N, and the data is transferred to multiplexer 6. At the same time, a collation is given between the parity received at circuit 12 and that generated newly to carry out the parity check, thus facilitating the switching to the auxiliary module.
JP11575778A 1978-09-22 1978-09-22 Test system for time-division channel Pending JPS5542441A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11575778A JPS5542441A (en) 1978-09-22 1978-09-22 Test system for time-division channel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11575778A JPS5542441A (en) 1978-09-22 1978-09-22 Test system for time-division channel

Publications (1)

Publication Number Publication Date
JPS5542441A true JPS5542441A (en) 1980-03-25

Family

ID=14670289

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11575778A Pending JPS5542441A (en) 1978-09-22 1978-09-22 Test system for time-division channel

Country Status (1)

Country Link
JP (1) JPS5542441A (en)

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