JPS5541600A - Multiplier - Google Patents
MultiplierInfo
- Publication number
- JPS5541600A JPS5541600A JP11917079A JP11917079A JPS5541600A JP S5541600 A JPS5541600 A JP S5541600A JP 11917079 A JP11917079 A JP 11917079A JP 11917079 A JP11917079 A JP 11917079A JP S5541600 A JPS5541600 A JP S5541600A
- Authority
- JP
- Japan
- Prior art keywords
- multiplier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
- G06F7/5306—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products
- G06F7/5312—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products using carry save adders
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
- G06F7/5324—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/386—Special constructional features
- G06F2207/3884—Pipelining
Landscapes
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computational Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL7809398A NL7809398A (nl) | 1978-09-15 | 1978-09-15 | Vermenigvuldiginrichting voor binaire getallen in twee-complement notatie. |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5541600A true JPS5541600A (en) | 1980-03-24 |
JPS6310450B2 JPS6310450B2 (ja) | 1988-03-07 |
Family
ID=19831544
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11917079A Granted JPS5541600A (en) | 1978-09-15 | 1979-09-17 | Multiplier |
Country Status (6)
Country | Link |
---|---|
US (1) | US4432066A (ja) |
JP (1) | JPS5541600A (ja) |
DE (1) | DE2936763A1 (ja) |
FR (1) | FR2436441B1 (ja) |
GB (1) | GB2030743B (ja) |
NL (1) | NL7809398A (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58181143A (ja) * | 1982-04-15 | 1983-10-22 | Matsushita Electric Ind Co Ltd | デイジタル乗算器 |
JPS58165312U (ja) * | 1982-04-30 | 1983-11-04 | 加藤発条株式会社 | 連結具 |
JPS59114634A (ja) * | 1982-12-15 | 1984-07-02 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | 乗算装置 |
JPS63108460A (ja) * | 1986-10-09 | 1988-05-13 | ゾ−ラン コ−ポレ−シヨン | ラツチされた和及びキヤリイを用いるマルチプライヤ回路 |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2524175A1 (fr) * | 1982-03-25 | 1983-09-30 | Labo Cent Telecommunicat | Structure de multiplieur rapide en circuit integre mos |
DE3482532D1 (de) * | 1983-07-06 | 1990-07-19 | Secr Defence Brit | Prozessor mit zwangseinstellung. |
US4748583A (en) * | 1984-09-17 | 1988-05-31 | Siemens Aktiengesellschaft | Cell-structured digital multiplier of semi-systolic construction |
US4736335A (en) * | 1984-11-13 | 1988-04-05 | Zoran Corporation | Multiplier-accumulator circuit using latched sums and carries |
US4706210A (en) * | 1984-12-13 | 1987-11-10 | The Johns Hopkins University | Guild array multiplier for binary numbers in two's complement notation |
US4750144A (en) * | 1985-12-31 | 1988-06-07 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Real time pipelined system for forming the sum of products in the processing of video data |
US4887233A (en) * | 1986-03-31 | 1989-12-12 | American Telephone And Telegraph Company, At&T Bell Laboratories | Pipeline arithmetic adder and multiplier |
US4831577A (en) * | 1986-09-17 | 1989-05-16 | Intersil, Inc. | Digital multiplier architecture with triple array summation of partial products |
US4768161A (en) * | 1986-11-14 | 1988-08-30 | International Business Machines Corporation | Digital binary array multipliers using inverting full adders |
US4796219A (en) * | 1987-06-01 | 1989-01-03 | Motorola, Inc. | Serial two's complement multiplier |
US4926371A (en) * | 1988-12-28 | 1990-05-15 | International Business Machines Corporation | Two's complement multiplication with a sign magnitude multiplier |
US7917559B2 (en) * | 2004-11-08 | 2011-03-29 | Tabula, Inc. | Configurable IC's with configurable logic circuits that perform adder and/or subtractor operations |
US7743085B2 (en) * | 2004-11-08 | 2010-06-22 | Tabula, Inc. | Configurable IC with large carry chains |
US7236009B1 (en) * | 2004-12-01 | 2007-06-26 | Andre Rohe | Operational time extension |
US8463836B1 (en) | 2005-11-07 | 2013-06-11 | Tabula, Inc. | Performing mathematical and logical operations in multiple sub-cycles |
US7765249B1 (en) | 2005-11-07 | 2010-07-27 | Tabula, Inc. | Use of hybrid interconnect/logic circuits for multiplication |
US7372297B1 (en) | 2005-11-07 | 2008-05-13 | Tabula Inc. | Hybrid interconnect/logic circuits enabling efficient replication of a function in several sub-cycles to save logic and routing resources |
US7818361B1 (en) * | 2005-11-07 | 2010-10-19 | Tabula, Inc. | Method and apparatus for performing two's complement multiplication |
US7679401B1 (en) * | 2005-12-01 | 2010-03-16 | Tabula, Inc. | User registers implemented with routing circuits in a configurable IC |
EP2597776A3 (en) * | 2007-03-20 | 2014-08-20 | Tabula, Inc. | Configurable IC having a routing fabric with storage elements |
US8863067B1 (en) | 2008-02-06 | 2014-10-14 | Tabula, Inc. | Sequential delay analysis by placement engines |
US8166435B2 (en) * | 2008-06-26 | 2012-04-24 | Tabula, Inc. | Timing operations in an IC with configurable circuits |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4990059A (ja) * | 1972-12-27 | 1974-08-28 | ||
JPS51115742A (en) * | 1975-04-03 | 1976-10-12 | Nec Corp | 2's complement parallel type multiplication circuit |
JPS52128026A (en) * | 1976-04-21 | 1977-10-27 | Nec Corp | Multi-input adding circuit for multiplication |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3469086A (en) * | 1964-10-09 | 1969-09-23 | Burroughs Corp | Majority logic multiplier circuit |
SE308413B (ja) * | 1967-06-30 | 1969-02-10 | Ibm Svenska Ab | |
US3670956A (en) * | 1968-09-26 | 1972-06-20 | Hughes Aircraft Co | Digital binary multiplier employing sum of cross products technique |
US3752971A (en) * | 1971-10-18 | 1973-08-14 | Hughes Aircraft Co | Expandable sum of cross product multiplier/adder module |
US3900724A (en) * | 1974-02-11 | 1975-08-19 | Trw Inc | Asynchronous binary multiplier using non-threshold logic |
US3947670A (en) * | 1974-11-22 | 1976-03-30 | General Electric Company | Signed multiplication logic |
US4130878A (en) * | 1978-04-03 | 1978-12-19 | Motorola, Inc. | Expandable 4 × 8 array multiplier |
-
1978
- 1978-09-15 NL NL7809398A patent/NL7809398A/nl not_active Application Discontinuation
-
1979
- 1979-09-12 DE DE19792936763 patent/DE2936763A1/de not_active Withdrawn
- 1979-09-12 GB GB7931615A patent/GB2030743B/en not_active Expired
- 1979-09-12 FR FR7922800A patent/FR2436441B1/fr not_active Expired
- 1979-09-17 JP JP11917079A patent/JPS5541600A/ja active Granted
-
1981
- 1981-07-13 US US06/282,887 patent/US4432066A/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4990059A (ja) * | 1972-12-27 | 1974-08-28 | ||
JPS51115742A (en) * | 1975-04-03 | 1976-10-12 | Nec Corp | 2's complement parallel type multiplication circuit |
JPS52128026A (en) * | 1976-04-21 | 1977-10-27 | Nec Corp | Multi-input adding circuit for multiplication |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58181143A (ja) * | 1982-04-15 | 1983-10-22 | Matsushita Electric Ind Co Ltd | デイジタル乗算器 |
JPS58165312U (ja) * | 1982-04-30 | 1983-11-04 | 加藤発条株式会社 | 連結具 |
JPS6214409Y2 (ja) * | 1982-04-30 | 1987-04-13 | ||
JPS59114634A (ja) * | 1982-12-15 | 1984-07-02 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | 乗算装置 |
JPS635774B2 (ja) * | 1982-12-15 | 1988-02-05 | Intaanashonaru Bijinesu Mashiinzu Corp | |
JPS63108460A (ja) * | 1986-10-09 | 1988-05-13 | ゾ−ラン コ−ポレ−シヨン | ラツチされた和及びキヤリイを用いるマルチプライヤ回路 |
Also Published As
Publication number | Publication date |
---|---|
US4432066A (en) | 1984-02-14 |
GB2030743B (en) | 1982-07-14 |
JPS6310450B2 (ja) | 1988-03-07 |
GB2030743A (en) | 1980-04-10 |
DE2936763A1 (de) | 1980-03-27 |
NL7809398A (nl) | 1980-03-18 |
FR2436441B1 (fr) | 1986-03-28 |
FR2436441A1 (fr) | 1980-04-11 |
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