JPS554114A - Synchronous detection circuit - Google Patents

Synchronous detection circuit

Info

Publication number
JPS554114A
JPS554114A JP7648078A JP7648078A JPS554114A JP S554114 A JPS554114 A JP S554114A JP 7648078 A JP7648078 A JP 7648078A JP 7648078 A JP7648078 A JP 7648078A JP S554114 A JPS554114 A JP S554114A
Authority
JP
Japan
Prior art keywords
signal
carrier
trs
modulated
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7648078A
Other languages
Japanese (ja)
Inventor
Seiichi Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7648078A priority Critical patent/JPS554114A/en
Publication of JPS554114A publication Critical patent/JPS554114A/en
Pending legal-status Critical Current

Links

Landscapes

  • Amplitude Modulation (AREA)
  • Television Receiver Circuits (AREA)

Abstract

PURPOSE: To prevent a tuning point from shifting by using a signal, obtained by passing the output of a tuning amplifier circuit through a multi-stage emitter follower circuit, as a signal synchronizing with a carrier when making detection by multiplying a modulated signal by the signal synchronizing with the carrier.
CONSTITUTION: Differential transistors Trs Q3 and Q4, and Q5 and Q6 provided to the collectors of transistors Q1 and Q2 amplifying modulated-wave signals mutually out of phase inputted from input terminals IN1 and IN2 constitute the switching circuit, which receives a signal synchronizing with a carrier at their bases and generates at their collectors a detection output obtained by multiplying the modulated-wave signal by the signal synchronizing with the carrier. Then, Trs Q1 and Q8 to be applied at their bases with this modulated-wave signal and tank circuit C.L tuned to a carrier frequency as the load of Trs Q9 and Q10 are provided, thereby constituting the tuning amplifier circuit which generates a signal synchronizing with the carrier. The output of this amplifier circuit is applied to the bases of Trs Q3 and Q4 through the two-stage emitter follower circuit composed of Trs Q11 to Q14, so that the tuning point can be prevented from shifting.
COPYRIGHT: (C)1980,JPO&Japio
JP7648078A 1978-06-26 1978-06-26 Synchronous detection circuit Pending JPS554114A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7648078A JPS554114A (en) 1978-06-26 1978-06-26 Synchronous detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7648078A JPS554114A (en) 1978-06-26 1978-06-26 Synchronous detection circuit

Publications (1)

Publication Number Publication Date
JPS554114A true JPS554114A (en) 1980-01-12

Family

ID=13606349

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7648078A Pending JPS554114A (en) 1978-06-26 1978-06-26 Synchronous detection circuit

Country Status (1)

Country Link
JP (1) JPS554114A (en)

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