JPS5540955B2 - - Google Patents

Info

Publication number
JPS5540955B2
JPS5540955B2 JP13834076A JP13834076A JPS5540955B2 JP S5540955 B2 JPS5540955 B2 JP S5540955B2 JP 13834076 A JP13834076 A JP 13834076A JP 13834076 A JP13834076 A JP 13834076A JP S5540955 B2 JPS5540955 B2 JP S5540955B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13834076A
Other versions
JPS5363938A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13834076A priority Critical patent/JPS5363938A/ja
Priority to US05/851,691 priority patent/US4118794A/en
Priority to DE19772751591 priority patent/DE2751591A1/de
Priority to NL7712819A priority patent/NL7712819A/xx
Publication of JPS5363938A publication Critical patent/JPS5363938A/ja
Publication of JPS5540955B2 publication Critical patent/JPS5540955B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
JP13834076A 1976-11-19 1976-11-19 Dynamic memory unit Granted JPS5363938A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP13834076A JPS5363938A (en) 1976-11-19 1976-11-19 Dynamic memory unit
US05/851,691 US4118794A (en) 1976-11-19 1977-11-15 Memory array with larger memory capacitors at row ends
DE19772751591 DE2751591A1 (de) 1976-11-19 1977-11-18 Dynamische speichereinrichtung
NL7712819A NL7712819A (nl) 1976-11-19 1977-11-21 Dynamische geheugeninrichting.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13834076A JPS5363938A (en) 1976-11-19 1976-11-19 Dynamic memory unit

Publications (2)

Publication Number Publication Date
JPS5363938A JPS5363938A (en) 1978-06-07
JPS5540955B2 true JPS5540955B2 (ja) 1980-10-21

Family

ID=15219617

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13834076A Granted JPS5363938A (en) 1976-11-19 1976-11-19 Dynamic memory unit

Country Status (4)

Country Link
US (1) US4118794A (ja)
JP (1) JPS5363938A (ja)
DE (1) DE2751591A1 (ja)
NL (1) NL7712819A (ja)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6041463B2 (ja) * 1976-11-19 1985-09-17 株式会社日立製作所 ダイナミツク記憶装置
US4195357A (en) * 1978-06-15 1980-03-25 Texas Instruments Incorporated Median spaced dummy cell layout for MOS random access memory
US4198697A (en) * 1978-06-15 1980-04-15 Texas Instruments Incorporated Multiple dummy cell layout for MOS random access memory
US4339766A (en) * 1979-10-11 1982-07-13 Texas Instruments Incorporated Dummy columns for reducing pattern sensitivity in MOS/LSI dynamic RAM
US4399520A (en) * 1980-02-22 1983-08-16 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor integrated circuit device
DE3101802A1 (de) * 1981-01-21 1982-08-19 Siemens AG, 1000 Berlin und 8000 München Monolithisch integrierter halbleiterspeicher
JPS6083293A (ja) * 1983-10-14 1985-05-11 Hitachi Micro Comput Eng Ltd ダイナミツク型ｒａｍ
US4665420A (en) * 1984-11-08 1987-05-12 Rca Corporation Edge passivated charge-coupled device image sensor
JPS643893A (en) * 1987-06-25 1989-01-09 Nec Corp Semiconductor storage device
JPH02146174A (ja) * 1988-11-28 1990-06-05 Nec Corp 半導体記憶装置
JP2836078B2 (ja) * 1988-12-27 1998-12-14 日本電気株式会社 半導体装置
US5237858A (en) * 1990-07-19 1993-08-24 Neotec Co., Inc. Method for determining the unhydration ratio of cement contained in cement sludge

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3760381A (en) * 1972-06-30 1973-09-18 Ibm Stored charge memory detection circuit
US4038646A (en) * 1976-03-12 1977-07-26 Intel Corporation Dynamic mos ram

Also Published As

Publication number Publication date
DE2751591A1 (de) 1978-05-24
NL7712819A (nl) 1978-05-23
US4118794A (en) 1978-10-03
JPS5363938A (en) 1978-06-07

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