JPS5539424A - Double tuned frequency discrimination circuit - Google Patents

Double tuned frequency discrimination circuit

Info

Publication number
JPS5539424A
JPS5539424A JP11231278A JP11231278A JPS5539424A JP S5539424 A JPS5539424 A JP S5539424A JP 11231278 A JP11231278 A JP 11231278A JP 11231278 A JP11231278 A JP 11231278A JP S5539424 A JPS5539424 A JP S5539424A
Authority
JP
Japan
Prior art keywords
circuit
input
output
becomes
band pass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11231278A
Other languages
Japanese (ja)
Inventor
Shunsuke Yoda
Tadamichi Kawasaki
Meiki Yahata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11231278A priority Critical patent/JPS5539424A/en
Publication of JPS5539424A publication Critical patent/JPS5539424A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To eliminate the complication of the circuit constitution by giving the frequency conversion to one of the two different input and then giving the frequency conversion also to one of two band pass filters.
CONSTITUTION: Input signal X or X' the amplitude modulation component of which is removed becomes the input of one side of 1st multiplier circuit 16. The other input of circuit 16 becomes the output of sine wave generation circuit 172 of constant generation circuit 171 selected by 1st switch 211 which is controlled by mode signal M. The output of circuit 16 becomes the input of one side of 2nd multilpier circuit 19 as well as scaler 18, and the output of scaler 18 is turned to be one input of subtractor circuit 25 via 1st band pass filter 22a, 1st absolute value circuit 23a and 1st band pass filter 24a each. And the other input of circuit 19 becomes the output of 2nd or 3rd sine wave generation circuit which is selected by 2nd switch 212, and the output of circuit 19 becomes the input of circuit 25 in the same way via circuits 22b, 23b and 24b each. The output of circuit 25 means detection output Y and Y'.
COPYRIGHT: (C)1980,JPO&Japio
JP11231278A 1978-09-14 1978-09-14 Double tuned frequency discrimination circuit Pending JPS5539424A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11231278A JPS5539424A (en) 1978-09-14 1978-09-14 Double tuned frequency discrimination circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11231278A JPS5539424A (en) 1978-09-14 1978-09-14 Double tuned frequency discrimination circuit

Publications (1)

Publication Number Publication Date
JPS5539424A true JPS5539424A (en) 1980-03-19

Family

ID=14583517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11231278A Pending JPS5539424A (en) 1978-09-14 1978-09-14 Double tuned frequency discrimination circuit

Country Status (1)

Country Link
JP (1) JPS5539424A (en)

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