JPS5539414A - Frame synchronous protecting system - Google Patents
Frame synchronous protecting systemInfo
- Publication number
- JPS5539414A JPS5539414A JP11173978A JP11173978A JPS5539414A JP S5539414 A JPS5539414 A JP S5539414A JP 11173978 A JP11173978 A JP 11173978A JP 11173978 A JP11173978 A JP 11173978A JP S5539414 A JPS5539414 A JP S5539414A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- end office
- given
- office
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To realize a frame synchronous protecting system which can cope with the phase jump with virtually no alteration of the design against the existing end office. CONSTITUTION:End office 10 is connected to other end office 20 via transmission line 30 and then furthermore to different end office via transmission lines 30' and 30'', thus forming the digital transmission network as a whole. For instance, bipolar digital signal Sa which is sent to office 10 via line 30' is changed to NRZ signal Sb within reception device 11 to be applied to memory 12. The reading is given to memory 12 by fundamental clock 55, and the frame clock is applied via line 56. Frame synchronization 42 is secured within device 11, and the step-out is counted via protective circuit 43. And the alarm is given when the count value exceeds a certain limit. In case the coincidence is obtained between the timing form signal lines 52 and 53 to memory 12 and the timing from signal lines 55 and 56, the phase shift is given forcedly to reset the memory to the normal operation as well as to make the information ineffective for that time.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11173978A JPS5539414A (en) | 1978-09-13 | 1978-09-13 | Frame synchronous protecting system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11173978A JPS5539414A (en) | 1978-09-13 | 1978-09-13 | Frame synchronous protecting system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5539414A true JPS5539414A (en) | 1980-03-19 |
Family
ID=14568950
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11173978A Pending JPS5539414A (en) | 1978-09-13 | 1978-09-13 | Frame synchronous protecting system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5539414A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6135173A (en) * | 1998-03-03 | 2000-10-24 | Samsung Electronics Co., Ltd. | Ice dispenser for refrigerator |
-
1978
- 1978-09-13 JP JP11173978A patent/JPS5539414A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6135173A (en) * | 1998-03-03 | 2000-10-24 | Samsung Electronics Co., Ltd. | Ice dispenser for refrigerator |
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