JPS5518726A - Microprogram controller - Google Patents

Microprogram controller

Info

Publication number
JPS5518726A
JPS5518726A JP9030178A JP9030178A JPS5518726A JP S5518726 A JPS5518726 A JP S5518726A JP 9030178 A JP9030178 A JP 9030178A JP 9030178 A JP9030178 A JP 9030178A JP S5518726 A JPS5518726 A JP S5518726A
Authority
JP
Japan
Prior art keywords
content
register
data
output bus
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9030178A
Other languages
Japanese (ja)
Inventor
Tadahiro Wada
Keiichi Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9030178A priority Critical patent/JPS5518726A/en
Publication of JPS5518726A publication Critical patent/JPS5518726A/en
Pending legal-status Critical Current

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  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: to make it possible to record a format signal on a medium by providing a circuit which making data on the output bus of an arithmetic circuit alternate between an odd number and even number according to the content of a parity control register provided with a microprogram.
CONSTITUTION: The output of FF11 having been set by a data request signal from encoder 9 is read out by the microprogram controller. Namely, a signal of "000000 001" is outputted to output bus 20 of arithmetic circuit 15. At the same time, the content of parity control register 12 is set to "1" and FF11 is reset. According to value "1" of the parity bit on output bus 20 and content "1" of control resister 12, EOR gate 13 outputs "0" and the parity bit of write data register 8 is set to "0". Therefore, a value of "000000000" is stored in register 8 and recorded on a medium after being transferred to write circuit 10. Here, encoder 9 sets FF11 again and requests next data. At the time of the arrival of an all-"1" signal, the output data on output bus 20 agree with the content of register 8.
COPYRIGHT: (C)1980,JPO&Japio
JP9030178A 1978-07-24 1978-07-24 Microprogram controller Pending JPS5518726A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9030178A JPS5518726A (en) 1978-07-24 1978-07-24 Microprogram controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9030178A JPS5518726A (en) 1978-07-24 1978-07-24 Microprogram controller

Publications (1)

Publication Number Publication Date
JPS5518726A true JPS5518726A (en) 1980-02-09

Family

ID=13994706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9030178A Pending JPS5518726A (en) 1978-07-24 1978-07-24 Microprogram controller

Country Status (1)

Country Link
JP (1) JPS5518726A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59151245A (en) * 1983-02-17 1984-08-29 Fujitsu Ltd Changing system of parity check

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59151245A (en) * 1983-02-17 1984-08-29 Fujitsu Ltd Changing system of parity check

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