JPS5517819A - Encoding procedure for recording and reproducing - Google Patents

Encoding procedure for recording and reproducing

Info

Publication number
JPS5517819A
JPS5517819A JP8878778A JP8878778A JPS5517819A JP S5517819 A JPS5517819 A JP S5517819A JP 8878778 A JP8878778 A JP 8878778A JP 8878778 A JP8878778 A JP 8878778A JP S5517819 A JPS5517819 A JP S5517819A
Authority
JP
Japan
Prior art keywords
array
parity
data
generated
sample
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8878778A
Other languages
Japanese (ja)
Inventor
Satoshi Kunii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8878778A priority Critical patent/JPS5517819A/en
Publication of JPS5517819A publication Critical patent/JPS5517819A/en
Pending legal-status Critical Current

Links

Landscapes

  • Error Detection And Correction (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE: To be able to correct up to the burst length of approximately twice the length of correction length by quantizating the 1st and 2nd analog signals L and R to binary codes after sampling them at a stated cycle and generating parity from the binary codes so that a block data stream can be constituted.
CONSTITUTION: The 1st and 2nd analog signals L and R are sampled respectively at a stated cycle and then are quantizated to binary codes. Parity P1 is generated from the respectively quantizated smaple data L1 and R1 an delayed parity array Pn-l, Pn-l+1... is generated by delaying parity array Pn, Pn+1... by l sample (2l<n). Moreover, the 1st composite sample array Ln, Rn+1, Ln+2... and the 2nd composite sample array Rn-2l, Ln+1-2l, Rn+2-2l... are generated by taking out sample data alternately from sample array Ln... and Rn... of respective signals. Thus, data are taken out one by one from the 3 kinds of data array, namely the 1st and 2nd composite sample array and the delayed parity array, and they are arrayed sequentially.
COPYRIGHT: (C)1980,JPO&Japio
JP8878778A 1978-07-20 1978-07-20 Encoding procedure for recording and reproducing Pending JPS5517819A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8878778A JPS5517819A (en) 1978-07-20 1978-07-20 Encoding procedure for recording and reproducing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8878778A JPS5517819A (en) 1978-07-20 1978-07-20 Encoding procedure for recording and reproducing

Publications (1)

Publication Number Publication Date
JPS5517819A true JPS5517819A (en) 1980-02-07

Family

ID=13952545

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8878778A Pending JPS5517819A (en) 1978-07-20 1978-07-20 Encoding procedure for recording and reproducing

Country Status (1)

Country Link
JP (1) JPS5517819A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02116204A (en) * 1988-10-25 1990-04-27 Matsushita Electric Ind Co Ltd High frequency amplifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02116204A (en) * 1988-10-25 1990-04-27 Matsushita Electric Ind Co Ltd High frequency amplifier

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