JPS55166756A - Electronic computer system - Google Patents

Electronic computer system

Info

Publication number
JPS55166756A
JPS55166756A JP7487579A JP7487579A JPS55166756A JP S55166756 A JPS55166756 A JP S55166756A JP 7487579 A JP7487579 A JP 7487579A JP 7487579 A JP7487579 A JP 7487579A JP S55166756 A JPS55166756 A JP S55166756A
Authority
JP
Japan
Prior art keywords
main memory
signal
reset
request
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7487579A
Other languages
Japanese (ja)
Inventor
Tadashi Iwase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7487579A priority Critical patent/JPS55166756A/en
Publication of JPS55166756A publication Critical patent/JPS55166756A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reset an operation hang-up state, occurring in main memory access operation between a main memory unit and information processor connected to it, without causing a secondary trouble by exercising a time supervision over a request signal by a time supervising circuit.
CONSTITUTION: Once request A for access to main memory unit 1a is generated by information processor 2a, F.F.21, when reset, is set to accept the request by access conflict control circuit 23 via main memory bus 5a and the request, when the 1st arrival, is made into signal RQC to set F.F.24, thereby generating a main memory drive signal. On the end of operation, F.F.21 and F.F. 24 are reset by data ready signal DRY from timing generation control circuit 25. However, when the DRY is not generated due to a fault, time supervising circuit 27 detects signal RQC not disappearing within a constant time to generate time-over error signal TOV, and then control circuit 23 and F.F.s 21 and 24 are reset to stop a hang-up state and also to report the error.
COPYRIGHT: (C)1980,JPO&Japio
JP7487579A 1979-06-14 1979-06-14 Electronic computer system Pending JPS55166756A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7487579A JPS55166756A (en) 1979-06-14 1979-06-14 Electronic computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7487579A JPS55166756A (en) 1979-06-14 1979-06-14 Electronic computer system

Publications (1)

Publication Number Publication Date
JPS55166756A true JPS55166756A (en) 1980-12-26

Family

ID=13559944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7487579A Pending JPS55166756A (en) 1979-06-14 1979-06-14 Electronic computer system

Country Status (1)

Country Link
JP (1) JPS55166756A (en)

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