JPS55166316A - Pulse duration modulating amplifier - Google Patents
Pulse duration modulating amplifierInfo
- Publication number
- JPS55166316A JPS55166316A JP7508179A JP7508179A JPS55166316A JP S55166316 A JPS55166316 A JP S55166316A JP 7508179 A JP7508179 A JP 7508179A JP 7508179 A JP7508179 A JP 7508179A JP S55166316 A JPS55166316 A JP S55166316A
- Authority
- JP
- Japan
- Prior art keywords
- trq5
- current
- circuits
- switching
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
PURPOSE:To simplify the constitution of the necessary muting function, by increasing enough the output voltage of the driver step forming a pulse modulating amplifier via the current switching logic circuit and at the same time securing the constant level for the output voltage to accelerate the rise and the fall. CONSTITUTION:Current switching logic (CML) circuits 10 and 11 are provided to produce the driving signals for output switching transistors (TR)Q3 and Q4 of the pulse duration modulating amplifier, and a pair of switching circuits comprising differential pairs TRQ5, Q6 plus Q7, Q8 are provided to circuits 10 and 11 each. Furthermore, constant current cources 5 and 6 are connected to the common emitter for TRQ5, Q6 plus Q7, Q8 each, and collector load resistances R4, R5 are connected to TRQ5, Q7 of one side. Then the fixed bias is applied to the bases of TRQ6, Q8 from the base bias circuit consisting of resistances R6, R7, R9, R8 each. And the current is supplied selectively to TRQ5, Q7 of one side in circuits 10 and 11 in accordance with the level of input signal B, and the current is supplied to TRQ6, Q8 via TRQ5, Q7. Thus the switching level is made constant for TRQ3, Q4 to ensure the assured control.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7508179A JPS55166316A (en) | 1979-06-14 | 1979-06-14 | Pulse duration modulating amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7508179A JPS55166316A (en) | 1979-06-14 | 1979-06-14 | Pulse duration modulating amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55166316A true JPS55166316A (en) | 1980-12-25 |
| JPS6121006B2 JPS6121006B2 (en) | 1986-05-24 |
Family
ID=13565866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7508179A Granted JPS55166316A (en) | 1979-06-14 | 1979-06-14 | Pulse duration modulating amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55166316A (en) |
-
1979
- 1979-06-14 JP JP7508179A patent/JPS55166316A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6121006B2 (en) | 1986-05-24 |
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