JPS55165015A - Delay line unit - Google Patents

Delay line unit

Info

Publication number
JPS55165015A
JPS55165015A JP7413379A JP7413379A JPS55165015A JP S55165015 A JPS55165015 A JP S55165015A JP 7413379 A JP7413379 A JP 7413379A JP 7413379 A JP7413379 A JP 7413379A JP S55165015 A JPS55165015 A JP S55165015A
Authority
JP
Japan
Prior art keywords
delay line
wiring
print pattern
cost
equivalent circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7413379A
Other languages
Japanese (ja)
Inventor
Hideo Matsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7413379A priority Critical patent/JPS55165015A/en
Publication of JPS55165015A publication Critical patent/JPS55165015A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/30—Time-delay networks
    • H03H7/34—Time-delay networks with lumped and distributed reactance

Landscapes

  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To reduce the cost and the occupied volume, by providing the fine print pattern on the surface of printed board, and providing the ground pattern at the back side opposing to the print pattern wiring. CONSTITUTION:The print pattern wiring 10 for delay line is provided on the surface of the printed board 9, and the ground pattern 11 is provided at the back of the board 9. The equivalent circuit is as shown. When a signal is input to the input terminal 4, it is fed to the wiring 10 and propagates the equivalent circuit as shown and the signal is output at the output terminal 6 with a delay time specified. Thus, the assembling of the components are unnecessary and the cost can be lowered, and the delay time can freely be changed. Further, the unit can be made flat and the occupied volume can be very small.
JP7413379A 1979-06-11 1979-06-11 Delay line unit Pending JPS55165015A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7413379A JPS55165015A (en) 1979-06-11 1979-06-11 Delay line unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7413379A JPS55165015A (en) 1979-06-11 1979-06-11 Delay line unit

Publications (1)

Publication Number Publication Date
JPS55165015A true JPS55165015A (en) 1980-12-23

Family

ID=13538379

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7413379A Pending JPS55165015A (en) 1979-06-11 1979-06-11 Delay line unit

Country Status (1)

Country Link
JP (1) JPS55165015A (en)

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