JPS55163615A - Writing compensating circuit - Google Patents

Writing compensating circuit

Info

Publication number
JPS55163615A
JPS55163615A JP7073979A JP7073979A JPS55163615A JP S55163615 A JPS55163615 A JP S55163615A JP 7073979 A JP7073979 A JP 7073979A JP 7073979 A JP7073979 A JP 7073979A JP S55163615 A JPS55163615 A JP S55163615A
Authority
JP
Japan
Prior art keywords
signal
circuit
terminal
delayed
reduce
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7073979A
Other languages
Japanese (ja)
Inventor
Kazuo Isaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7073979A priority Critical patent/JPS55163615A/en
Publication of JPS55163615A publication Critical patent/JPS55163615A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To ensure the correction so as to reduce the extent of phase shift at the reproducing time, by providing the identifying means for the continuous data of the bit pattern, the delay means to reduce the voltage peak shift occurring to the reproduction head, and the means to produce the writing signal in the delayed timing.
CONSTITUTION: The input signal is supplied through terminal 1 and then delayed by 2-unit time via delay FF7, 8. The synchronous clock signal supplied through input terminal 2 is applied to terminals T of FF7, 8 each as well as to various- type delay clock generating circuit 3 to be converted into various types of delayed clocks. Data identifying circuit 4 gives the collation between the signal supplied to terminal 1 and the output signal of FF8. And the clock signal suited to the combination among the delayed clocks is selected through circuit 3 and then applied to writing signal producing circuit 5. Circuit 5 delivers the signal corrected to reduce the phase shift at the reproducing time to output terminal 6.
COPYRIGHT: (C)1980,JPO&Japio
JP7073979A 1979-06-06 1979-06-06 Writing compensating circuit Pending JPS55163615A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7073979A JPS55163615A (en) 1979-06-06 1979-06-06 Writing compensating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7073979A JPS55163615A (en) 1979-06-06 1979-06-06 Writing compensating circuit

Publications (1)

Publication Number Publication Date
JPS55163615A true JPS55163615A (en) 1980-12-19

Family

ID=13440177

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7073979A Pending JPS55163615A (en) 1979-06-06 1979-06-06 Writing compensating circuit

Country Status (1)

Country Link
JP (1) JPS55163615A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5712405A (en) * 1980-06-23 1982-01-22 Nec Corp Write timing compensating system of magnetic recording device
JPS6015868A (en) * 1983-07-06 1985-01-26 Fujitsu Ltd Malfunction detecting method of write correcting circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50102312A (en) * 1973-12-28 1975-08-13
JPS5216938A (en) * 1975-07-28 1977-02-08 Computer Peripherals Method and device for recording data
JPS5357013A (en) * 1976-11-02 1978-05-24 Nec Corp Digital type magnetic recording system
JPS53102007A (en) * 1977-02-18 1978-09-06 Hitachi Ltd Agnetic memory device
JPS5422514A (en) * 1977-07-21 1979-02-20 Nippon Denso Co Ltd Control device of motor which has shunt field winding

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50102312A (en) * 1973-12-28 1975-08-13
JPS5216938A (en) * 1975-07-28 1977-02-08 Computer Peripherals Method and device for recording data
JPS5357013A (en) * 1976-11-02 1978-05-24 Nec Corp Digital type magnetic recording system
JPS53102007A (en) * 1977-02-18 1978-09-06 Hitachi Ltd Agnetic memory device
JPS5422514A (en) * 1977-07-21 1979-02-20 Nippon Denso Co Ltd Control device of motor which has shunt field winding

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5712405A (en) * 1980-06-23 1982-01-22 Nec Corp Write timing compensating system of magnetic recording device
JPS6015868A (en) * 1983-07-06 1985-01-26 Fujitsu Ltd Malfunction detecting method of write correcting circuit
JPH0574125B2 (en) * 1983-07-06 1993-10-15 Fujitsu Ltd

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