JPH0574125B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention corrects the peak shift on the magnetic recording medium by adjusting the magnetization reversal interval of the written data when writing data to the magnetic recording medium in a magnetic recording device. The present invention relates to a write data correction circuit configured to shift in advance as described above, and particularly relates to a write data correction circuit that allows a failure of the write data correction circuit to be detected with a simple circuit.

(b) Prior Art and Problems Correction of write data in a magnetic recording device involves magnetization reversal using a write current in advance in order to correct the peak shift that occurs when reading the write data when writing data to a magnetic recording medium. For example, recording by shifting the position of the interval is
This is generally practiced as disclosed in Japanese Patent Application Laid-open No. 163615 and Japanese Patent Application Laid-Open No. 102312/1983.

The occurrence of this peak shift is determined by the magnetization reversal pattern of the written data. For this reason, the write data correction circuit usually uses at least three clocks with different phases.

That is, the clock φ1 that causes magnetization reversal at the normal position
A clock φ2 whose phase is ahead of the clock φ1 and a clock φ3 whose phase is delayed from the clock φ1 are prepared, and the clock is selected depending on the current polarity judgment status of the data to be written to determine the timing of the write current polarity. Corrections are being made.

FIG. 1 is a block diagram showing an example of a write data correction circuit used in conventional write pattern correction, and FIG. 2 is a diagram illustrating the relationship between the clock of FIG. 1 and the phase of write current polarity.

Write data is input from terminal A and written into register 1 using the clock input from terminal B as timing. Then, the pattern determination circuit 2 determines whether the data read from the register 1 causes a peak shift at the magnetization reversal position compared to the adjacent written data, or whether the magnetization reversal is isolated and is not affected by the peak shift. As a result, it is determined whether the phase of the write data needs to be delayed or advanced in order to compensate for this peak shift.

Based on this determination, the pattern determination circuit 2 outputs a signal for selecting one of the selection circuits 3, 4, and 5. From terminal C, clock φ1 is
Clock φ2 is input from terminal D, and clock φ3 is input from terminal E. As shown in FIG. 2, φ1 is a clock for magnetization reversal at the normal position, φ2 is a clock whose phase is ahead of φ1 by Δt1 time, and φ3 is a clock whose phase is delayed by Δt2 time from φ1. The output of one of the selection circuits 3, 4, and 5 selected according to the above conditions is inputted to the T terminal of the JK flip-flop 7 via the OR circuit 6. Since the J and K terminals of the JK flip-flop 7 are connected to the power supply, they are repeatedly set and reset by the rising edge of the clock input from any of the selection circuits 3, 4, and 5, and a write current signal is sent from the terminal F. be done. Therefore, for example,
When the selection circuit 3 is selected, the write current sent from the terminal F, whose magnetization is reversed at the normal position, reverses its polarity at the rising edge of the clock φ1, as shown in FIG. 2a.

In such a write data correction circuit, if a failure occurs somewhere in the pattern judgment circuit 2 or the selection circuit 4 and the clock φ2 continues to be sent, the clock indicated by φ4 is sent to the JK flip-flop 7. It becomes like this. In this case, writing is performed with all of the write data being advanced in phase. That is, as shown in FIG. 2b, the time Δt1 phase always advances. Also, a failure occurs somewhere in the pattern judgment circuit 2 and the selection circuit 3, causing the clock φ1 to fail.
If it continues to be sent out, the clock indicated by φ5 enters the flip-flop 7, and the data to be written is also written at the normal position with a phase delay of time Δt2. Therefore, magnetic recording is performed with a small margin.

Therefore, data with a small margin is recorded on the recording medium. In general, correction of written data is particularly effective when abnormal conditions such as dropouts occur, and recording media such as magnetic tape devices that have been recorded under the above abnormal conditions cannot accurately reproduce data during normal reading. It is difficult to carry out this method, and in the abnormal state described above, there is a drawback that a large number of magnetic recording media with small margins are produced.

As a method to solve these problems, for example, as disclosed in Japanese Patent Application Laid-open No. 102312/1983,
The write data correction circuit detects an abnormality when all the outputs of the pattern determination circuit become low level at the same time, and provides a determination circuit that determines whether two arbitrary signals in the selection circuit are output at the same time. However, these methods have the problem that the circuit for detecting the abnormality is complicated and the write data correction circuit is expensive.

(c) Object of the Invention In order to solve the above-mentioned drawbacks, an object of the present invention is to configure a write data correction circuit so that a fault can be detected during writing with an extremely simple circuit, thereby reducing the error margin. An object of the present invention is to provide a write data correction circuit that can prevent data from being written to a magnetic recording medium.

(d) Structure of the Invention The present invention provides a pattern determination circuit that determines a pattern of data to be written on a magnetic recording medium and outputs a plurality of signals indicating the data and its direction whose write timing should be corrected; It is composed of a judgment result output of a judgment circuit and a plurality of selection circuits into which clocks having different phases are respectively input, and one of the plurality of clocks is selected and output according to the output of the pattern judgment circuit. The write data correction circuit is configured to shift the magnetization reversal interval of write data in advance so as to correct a peak shift on a magnetic recording medium due to an abnormality in the selection circuit or the pattern determination circuit. When clocks are simultaneously output from at least two selection circuits, an exclusive OR gate is provided between each selection circuit to create write data with a frequency higher than the frequency of the original write data by utilizing the overlap of the clocks. The write data correction circuit is configured such that the output thereof is used as write data.

With this configuration, the present invention can improve the conventional
By simply adding an exclusive OR circuit instead of an OR circuit, data with a high frequency that cannot normally be written is written on the recording medium, and a read check at the time of writing ensures reliability. Since it is possible to generate a write error in the correction circuit, it is possible to accurately detect an abnormality in the correction circuit with an extremely simple circuit.

(e) Embodiments of the Invention The present invention uses an exclusive OR circuit in place of the OR circuit 6 in FIG. The magnetization reversal frequency of the write data is 2.
This makes it possible to detect a write error by a read check during writing.

FIG. 3 is a block diagram of a circuit showing one embodiment of the present invention. FIG. 4 is a diagram illustrating the relationship between the clock of FIG. 3 and the phase of write current polarity. Register 1, pattern determination circuit 2, selection circuit 3,
The operations 4 and 5 are the same as in FIG. Selection circuit 3
The outputs of and 4 enter the exclusive OR circuit 8, and the output of the selection circuit 5 and the output of the exclusive OR circuit 8 are exclusive
Enters OR circuit 9. Therefore, some part of the pattern inversion circuit 2 and selection circuit 4 becomes a failure, and the clock φ
2 remains sent out, the output of the exclusive OR circuit 8 is divided into two clock pulses for one output, as shown at φ6 in FIG. Therefore, the write data indicated by e is sent to the output terminal F of the flip-flop 7 by the clock φ6 which enters the flip-flop 7 via the exclusive OR circuit 9, and unlike the waveform shown in FIG. 2a, the magnetization reversal interval is becomes narrower and the writing frequency becomes higher. Therefore, when data is recorded on a recording medium at such magnetization reversal intervals, a write error is reliably detected by a read check during writing.

Furthermore, if the clock φ1 continues to be sent, when the selection circuit 5 is selected, the clock indicated by φ7 is output to the exclusive OR circuit 9, and the output F of the flip-flop 7 receives the write current output by f. and is reliably detected as a write error in the same way as before.

(f) Effects of the Invention As explained above, the write data correction circuit of the present invention uses an exclusive OR circuit instead of a conventional OR circuit.
By simply applying an OR circuit, it is possible to reliably detect a failure in the write data correction circuit as a write error through a read check during writing, and with a very simple circuit, it is possible to erroneously correct data with a small margin like in the past. It is possible to prevent a situation in which writing is done on a recording medium and then left unattended, and the effect is great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a write data correction circuit used in conventional pattern correction, FIG. 2 is a diagram illustrating the relationship between the clock in FIG. 1 and the phase of the write current polarity, and FIG. 3 is a diagram showing the present invention. FIG. 4 is a block diagram of a circuit showing one embodiment of the present invention, and is a diagram for explaining the relationship between the clock of FIG. 3 and the phase of the write current polarity. In the figure, 1 is a register, 2 is a pattern determination circuit, 3, 4, and 5 are selection circuits, 7 is a flip-flop, and 8 and 9 are exclusive OR circuits, respectively.

Claims (1)

[Scope of Claims] 1. A pattern determination circuit that determines a pattern of data to be written on a magnetic recording medium and outputs a plurality of signals indicating the data and its direction whose write timing should be corrected; It is composed of a judgment result output and a plurality of selection circuits into which clocks having different phases are respectively input, and one of the plurality of clocks is selected and output according to the output of the pattern judgment circuit. A write data correction circuit configured to shift the magnetization reversal interval of write data in advance so as to correct a peak shift on a magnetic recording medium, wherein the write data correction circuit is configured to shift the magnetization reversal interval of write data in advance so as to correct a peak shift on a magnetic recording medium, When clocks are output from two selection circuits simultaneously, an exclusive OR gate is provided between each of the selection circuits to create write data with a frequency higher than the frequency of the original write data by utilizing the overlap of the clocks. A write data correction circuit characterized in that the output is used as write data.