JPS55161424A - Pulse amplifier - Google Patents

Pulse amplifier

Info

Publication number
JPS55161424A
JPS55161424A JP6909679A JP6909679A JPS55161424A JP S55161424 A JPS55161424 A JP S55161424A JP 6909679 A JP6909679 A JP 6909679A JP 6909679 A JP6909679 A JP 6909679A JP S55161424 A JPS55161424 A JP S55161424A
Authority
JP
Japan
Prior art keywords
signal
circuit
voltage
amplified
operation mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6909679A
Other languages
Japanese (ja)
Inventor
Shigenori Kodama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6909679A priority Critical patent/JPS55161424A/en
Publication of JPS55161424A publication Critical patent/JPS55161424A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To prevent malfunctions dependent upon minute noise to reduce probability of self-oscillation, by rectifying the output voltage from the output end and by feeding back it to the input terminal and by connecting a reference voltage circuit to another input end of a differential amplifying circuit or a rectifying circuit. CONSTITUTION:Difference voltage V1-V2 between voltage signal V1 obtained by synthesizing the input voltage signal from the first external terminal 11 and the reference voltage signal from reference voltage circuit 18 and rectified voltage signal V2 of output voltage signal V0 of differential amplifying circuit 10 is amplified by circuit 10 to obtain signal V0. In operation mode A, signal V0=V0a is DC. In operation mode B, signal V1b is amplified by circuit 10 to obtain signal V0=V0b. In operation mode C, signal V1c is amplified by circuit 10 to obtain signal V0=V0c.
JP6909679A 1979-06-01 1979-06-01 Pulse amplifier Pending JPS55161424A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6909679A JPS55161424A (en) 1979-06-01 1979-06-01 Pulse amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6909679A JPS55161424A (en) 1979-06-01 1979-06-01 Pulse amplifier

Publications (1)

Publication Number Publication Date
JPS55161424A true JPS55161424A (en) 1980-12-16

Family

ID=13392730

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6909679A Pending JPS55161424A (en) 1979-06-01 1979-06-01 Pulse amplifier

Country Status (1)

Country Link
JP (1) JPS55161424A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006127731A (en) * 2004-10-30 2006-05-18 Hynix Semiconductor Inc Data input/output driver of semiconductor memory device and its drive method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006127731A (en) * 2004-10-30 2006-05-18 Hynix Semiconductor Inc Data input/output driver of semiconductor memory device and its drive method

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